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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td172 def maskzeroupperv32i1 : maskzeroupper<v32i1, VK32>;
178 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
181 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
184 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
236 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
239 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
296 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
304 (v32i1 VK32:$mask), (iPTR 0))),
309 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
321 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
[all …]
DX86CallingConv.td84 // Promote v8i1/v16i1/v32i1 arguments to i32.
85 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>,
161 // Promote v32i1 arguments to i32.
162 CCIfType<[v32i1], CCPromoteToType<i32>>,
230 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
538 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
823 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrVecCompiler.td172 def maskzeroupperv32i1 : maskzeroupper<v32i1, VK32>;
178 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
181 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
184 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
236 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
239 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
296 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
304 (v32i1 VK32:$mask), (iPTR 0))),
309 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
321 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
[all …]
DX86CallingConv.td84 // Promote v8i1/v16i1/v32i1 arguments to i32.
85 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>,
161 // Promote v32i1 arguments to i32.
162 CCIfType<[v32i1], CCPromoteToType<i32>>,
230 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
544 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
830 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
DX86TargetTransformInfo.cpp1428 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, in getCastInstrCost()
1429 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, in getCastInstrCost()
1441 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, in getCastInstrCost()
1442 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, in getCastInstrCost()
1455 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm in getCastInstrCost()
1456 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, in getCastInstrCost()
1603 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, in getCastInstrCost()
1614 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, in getCastInstrCost()
1625 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb in getCastInstrCost()
3433 { ISD::AND, MVT::v32i1, 11 }, in getArithmeticReductionCost()
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h63 v32i1 = 17, // 32 x i1 enumerator
321 case v32i1: in getVectorElementType()
384 case v32i1: in getVectorNumElements()
461 case v32i1: in getSizeInBits()
597 if (NumElements == 32) return MVT::v32i1; in getVectorVT()
DValueTypes.td40 def v32i1 : ValueType<32 , 17>; // 32 x i1 vector value
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h65 v32i1 = 19, // 32 x i1 enumerator
335 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 || in is32BitVector()
433 case v32i1: in getVectorElementType()
573 case v32i1: in getVectorNumElements()
720 case v32i1: in getSizeInBits()
928 if (NumElements == 32) return MVT::v32i1; in getVectorVT()
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dvecreduce-bool.ll9 declare i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %a)
16 declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %a)
108 %y = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %x)
203 %y = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %x)
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h66 v32i1 = 20, // 32 x i1 enumerator
364 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 || in is32BitVector()
500 case v32i1: in getVectorElementType()
678 case v32i1: in getVectorNumElements()
846 case v32i1: in getSizeInBits()
1115 if (NumElements == 32) return MVT::v32i1; in getVectorVT()
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dreduce-xor.ll162 …estimated cost of 46 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
173 …estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
184 …estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
195 …estimated cost of 46 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
206 …estimated cost of 26 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
217 …stimated cost of 134 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
228 …stimated cost of 326 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
239 …stimated cost of 134 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
249 %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
287 declare i1 @llvm.vector.reduce.xor.v32i1(<32 x i1>)
Dreduce-or.ll162 …n estimated cost of 3 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
173 …n estimated cost of 4 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
184 …n estimated cost of 2 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
195 … estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
206 … estimated cost of 11 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
217 … estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
227 %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
265 declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1>)
Dreduce-and.ll162 … estimated cost of 3 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
173 … estimated cost of 4 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
184 … estimated cost of 2 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
195 …estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
206 …estimated cost of 11 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
217 …estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
227 %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
265 declare i1 @llvm.vector.reduce.and.v32i1(<32 x i1>)
/external/llvm-project/llvm/test/CodeGen/X86/
Dpr47299.ll6 declare <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64, i64)
83 %2 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 0, i64 %0)
Davx512-regcall-Mask.ll281 ; Test regcall when receiving arguments of v32i1 type
402 ; Test regcall when passing arguments of v32i1 type
454 ; Test regcall when returning v32i1 type
469 ; Test regcall when processing result of v32i1 type
Dvector-reduce-and-bool.ll495 %b = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %a)
768 %b = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %a)
1357 %b = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %a)
1598 %b = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %a)
1697 declare i1 @llvm.vector.reduce.and.v32i1(<32 x i1>)
Dvector-reduce-or-bool.ll482 %b = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %a)
751 %b = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %a)
1344 %b = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %a)
1590 %b = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %a)
1691 declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1>)
/external/llvm/lib/IR/
DValueTypes.cpp149 case MVT::v32i1: return "v32i1"; in getEVTString()
227 case MVT::v32i1: return VectorType::get(Type::getInt1Ty(Context), 32); in getTypeForEVT()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td304 [v32i1, v64i1, v32i1]>;
306 [v16i1, v32i1, v16i1]>;
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td340 [v32i1, v64i1, v32i1]>;
342 [v16i1, v32i1, v16i1]>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenDAGISel.inc7146 /* 15339*/ OPC_CheckChild1Type, MVT::v32i1,
7155 …// Src: (st VK32:{ *:[v32i1] }:$src, addr:{ *:[iPTR] }:$dst)<<P:Predicate_unindexedstore>><<P:Pred…
7156 // Dst: (KMOVDmk addr:{ *:[iPTR] }:$dst, VK32:{ *:[v32i1] }:$src)
8496 /* 18264*/ OPC_CheckChild4Type, MVT::v32i1,
8504 …[v32i8] }:$src, addr:{ *:[iPTR] }:$ptr, (undef:{ *:[iPTR] }), VK32WM:{ *:[v32i1] }:$mask)<<P:Predi…
8505 …// Dst: (VMOVDQU8Z256mrk addr:{ *:[iPTR] }:$ptr, VK32WM:{ *:[v32i1] }:$mask, VR256X:{ *:[v32i8] }:…
8513 …[v32i8] }:$src, addr:{ *:[iPTR] }:$dst, (undef:{ *:[iPTR] }), VK32WM:{ *:[v32i1] }:$mask)<<P:Predi…
8514 …// Dst: (VPCOMPRESSBZ256mrk addr:{ *:[iPTR] }:$dst, VK32WM:{ *:[v32i1] }:$mask, VR256X:{ *:[v32i8]…
8550 /* 18376*/ OPC_CheckChild4Type, MVT::v32i1,
8558 …v32i16] }:$src, addr:{ *:[iPTR] }:$ptr, (undef:{ *:[iPTR] }), VK32WM:{ *:[v32i1] }:$mask)<<P:Predi…
[all …]
DX86GenCallingConv.inc521 if (LocVT == MVT::v32i1) {
822 LocVT == MVT::v32i1) {
1519 if (LocVT == MVT::v32i1) {
1888 LocVT == MVT::v32i1) {
2359 LocVT == MVT::v32i1) {
2766 if (LocVT == MVT::v32i1) {
3047 if (LocVT == MVT::v32i1) {
3617 if (LocVT == MVT::v32i1) {
3831 if (LocVT == MVT::v32i1) {
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp77 case MVT::v32i1: return "MVT::v32i1"; in getEnumName()
/external/llvm/lib/Target/X86/
DX86CallingConv.td50 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
327 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
600 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
DX86RegisterInfo.td516 def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
524 def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}

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