Home
last modified time | relevance | path

Searched refs:v3i32 (Results 1 – 25 of 77) sorted by relevance

1234

/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.tbuffer.store.dwordx3.ll8 …call void @llvm.amdgcn.raw.tbuffer.store.v3i32(<3 x i32> %in1, <4 x i32> %0, i32 42, i32 0, i32 11…
19 …call void @llvm.amdgcn.struct.tbuffer.store.v3i32(<3 x i32> %in1, <4 x i32> %0, i32 0, i32 42, i32…
28 …call void @llvm.amdgcn.tbuffer.store.v3i32(<3 x i32> %in1, <4 x i32> %0, i32 0, i32 0, i32 0, i32 …
32 declare void @llvm.amdgcn.raw.tbuffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32, i32) #0
33 declare void @llvm.amdgcn.struct.tbuffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32, i32, i32)…
34 declare void @llvm.amdgcn.tbuffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i…
Dllvm.amdgcn.tbuffer.load.dwordx3.ll9 …%vdata = call <3 x i32> @llvm.amdgcn.raw.tbuffer.load.v3i32(<4 x i32> %0, i32 42, i32 0, i32 78,…
21 …%vdata = call <3 x i32> @llvm.amdgcn.struct.tbuffer.load.v3i32(<4 x i32> %0, i32 0, i32 42, i32 …
32 …%vdata = call <3 x i32> @llvm.amdgcn.tbuffer.load.v3i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 4…
37 declare <3 x i32> @llvm.amdgcn.raw.tbuffer.load.v3i32(<4 x i32>, i32, i32, i32, i32)
38 declare <3 x i32> @llvm.amdgcn.struct.tbuffer.load.v3i32(<4 x i32>, i32, i32, i32, i32, i32)
39 declare <3 x i32> @llvm.amdgcn.tbuffer.load.v3i32(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
Dextract_subvector_vec4_vec3.ll31 …call void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32> %tmp29, <4 x i32> undef, i32 undef, i32 0,…
35 declare void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32 immarg)
Dpromote-vect3-load.ll3 ; The type promotion for the vector loads v3i32/v3f32 into v4i32/v4f32 is enabled
Dllvm.amdgcn.s.buffer.load.ll88 %load = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> %desc, i32 64, i32 0)
102 %load = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> %desc, i32 %index, i32 0)
118 %load = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> %desc, i32 %index, i32 0)
459 declare <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32>, i32, i32)
/external/llvm-project/llvm/test/Instrumentation/MemorySanitizer/
Dreduce.ll20 ; CHECK: [[R_SHADOW:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[O_SHADOW]])
21 ; CHECK: [[R:%.*]] = call i32 @llvm.vector.reduce.add.v3i32(<3 x i32> [[O]])
38 ; CHECK: [[O_SHADOW_2:%.*]] = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> [[O_SHADOW_1]]
39 ; CHECK: [[O_SHADOW_3:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[O_SHADOW]])
41 ; CHECK: [[R:%.*]] = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> [[O]])
59 ; CHECK: [[O_SHADOW_2:%.*]] = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> [[O_SHADOW_1]]
60 ; CHECK: [[O_SHADOW_3:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[O_SHADOW]])
62 ; CHECK: [[R:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[O]])
/external/llvm-project/llvm/test/CodeGen/X86/
Dload-local-v3i1.ll10 declare <3 x i32> @llvm.masked.load.v3i32.p1v3i32(<3 x i32> addrspace(1)*, i32, <3 x i1>, <3 x i32>)
13 declare void @llvm.masked.store.v3i32.p1v3i32(<3 x i32>, <3 x i32> addrspace(1)*, i32, <3 x i1>)
49 …%3 = call <3 x i32> @llvm.masked.load.v3i32.p1v3i32(<3 x i32> addrspace(1)* %2, i32 4, <3 x i1> %1…
86 …call void @llvm.masked.store.v3i32.p1v3i32(<3 x i32> %0, <3 x i32> addrspace(1)* %3, i32 4, <3 x i…
Dwiden_cast-3.ll5 ; bitcast v12i8 to v3i32
Dwiden_arith-5.ll4 ; widen a v3i32 to v4i32 to do a vector multiple and a subtraction
Dwiden_conv-1.ll31 ; truncate v3i32 to v3i8
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dcanonicalize-vector-extract.ll9 declare <3 x i32> @llvm.experimental.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 %idx)
90 %1 = call <3 x i32> @llvm.experimental.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 0)
99 %1 = call <3 x i32> @llvm.experimental.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 3)
Dcanonicalize-vector-insert.ll8 declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec, i…
97 …%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec…
107 …%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec…
/external/llvm/test/CodeGen/X86/
Dwiden_cast-3.ll6 ; bitcast v12i8 to v3i32
Dwiden_arith-5.ll6 ; widen a v3i32 to v4i32 to do a vector multiple and a subtraction
Dwiden_conv-1.ll29 ; truncate v3i32 to v3i8
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h94 v3i32 = 45, // 3 x i32 enumerator
477 case v3i32: in getVectorElementType()
633 case v3i32: in getVectorNumElements()
753 case v3i32: in getSizeInBits()
960 if (NumElements == 3) return MVT::v3i32; in getVectorVT()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCallingConv.td39 CCIfType<[v3i32, v3f32], CCAssignToStack<12, 4>>,
80 CCIfType<[v3i32, v3f32], CCAssignToStack<12, 4>>,
210 CCIfType<[v3i32, v3f32], CCAssignToStack<12, 4>>,
DBUFInstructions.td820 "buffer_load_format_d16_xyz", v3i32
832 "buffer_store_format_d16_xyz", v3i32
885 "buffer_load_dwordx3", v3i32
899 defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_DWORDX3", v3i32, load_global>;
910 "buffer_load_dwordx3", v3i32, null_frag, 0, 1
930 "buffer_store_dwordx3", v3i32, store_global
1214 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v3i32, "BUFFER_LOAD_FORMAT_XYZ">;
1223 …defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, v3i32, "BUFFER_LOAD_FORMAT_D16_XYZ_gfx80">;
1248 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v3i32, "BUFFER_LOAD_DWORDX3">;
1303 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v3i32, "BUFFER_STORE_FORMAT_XYZ">;
[all …]
DSIRegisterInfo.td690 def SGPR_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32,
695 def SReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32,
801 def VReg_96 : VRegClass<3, [v3i32, v3f32], (add VGPR_96)>;
817 def AReg_96 : ARegClass<3, [v3i32, v3f32], (add AGPR_96)>;
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h95 v3i32 = 46, // 3 x i32 enumerator
546 case v3i32: in getVectorElementType()
748 case v3i32: in getVectorNumElements()
885 case v3i32: in getSizeInBits()
1147 if (NumElements == 3) return MVT::v3i32; in getVectorVT()
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dvecreduce-add-legalization.ll14 declare i32 @llvm.vector.reduce.add.v3i32(<3 x i32> %a)
123 %b = call i32 @llvm.vector.reduce.add.v3i32(<3 x i32> %a)
Dvecreduce-umax-legalization.ll15 declare i32 @llvm.vector.reduce.umax.v3i32(<3 x i32> %a)
138 %b = call i32 @llvm.vector.reduce.umax.v3i32(<3 x i32> %a)
Dvecreduce-and-legalization.ll14 declare i32 @llvm.vector.reduce.and.v3i32(<3 x i32> %a)
136 %b = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> %a)
/external/llvm-project/llvm/test/Analysis/CostModel/AMDGPU/
Dadd-sub.ll26 ; Allow for 4 when v3i32 is illegal and TargetLowering thinks it needs widening,
46 ; Allow for 8 when v3i32 is illegal and TargetLowering thinks it needs widening,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DBUFInstructions.td812 "buffer_load_format_d16_xyz", v3i32
824 "buffer_store_format_d16_xyz", v3i32
877 "buffer_load_dwordx3", v3i32
891 defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_DWORDX3", v3i32, load_global>;
902 "buffer_load_dwordx3", v3i32, null_frag, 0, 1
922 "buffer_store_dwordx3", v3i32, store_global
1217 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v3i32, "BUFFER_LOAD_FORMAT_XYZ">;
1246 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v3i32, "BUFFER_LOAD_DWORDX3">;
1299 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v3i32, "BUFFER_STORE_FORMAT_XYZ">;
1328 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v3i32, "BUFFER_STORE_DWORDX3">;
[all …]

1234