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Searched refs:v5f32 (Results 1 – 25 of 25) sorted by relevance

/external/llvm-project/llvm/test/Analysis/CostModel/AMDGPU/
Dfma.ll40 ; SLOWF32: estimated cost of 20 for {{.*}} call <5 x float> @llvm.fma.v5f32
41 ; FASTF32: estimated cost of 10 for {{.*}} call <5 x float> @llvm.fma.v5f32
42 ; SIZEALL: estimated cost of 10 for {{.*}} call <5 x float> @llvm.fma.v5f32
45 %fma = call <5 x float> @llvm.fma.v5f32(<5 x float> %vec, <5 x float> %vec, <5 x float> %vec) #1
121 declare <5 x float> @llvm.fma.v5f32(<5 x float>, <5 x float>, <5 x float>) #1
Dfabs.ll32 ; CHECK: estimated cost of 0 for {{.*}} call <5 x float> @llvm.fabs.v5f32
35 %fabs = call <5 x float> @llvm.fabs.v5f32(<5 x float> %vec) #1
97 declare <5 x float> @llvm.fabs.v5f32(<5 x float>) #1
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h129 v5f32 = 74, // 5 x f32 enumerator
521 case v5f32: in getVectorElementType()
615 case v5f32: return 5; in getVectorNumElements()
775 case v5f32: return TypeSize::Fixed(160); in getSizeInBits()
997 if (NumElements == 5) return MVT::v5f32; in getVectorVT()
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dvecreduce-fadd-legalization.ll10 declare float @llvm.vector.reduce.fadd.f32.v5f32(float, <5 x float>)
80 %b = call reassoc float @llvm.vector.reduce.fadd.f32.v5f32(float -0.0, <5 x float> %a)
Dvecreduce-fadd-legalization-strict.ll12 declare float @llvm.vector.reduce.fadd.f32.v5f32(float, <5 x float>)
128 %b = call float @llvm.vector.reduce.fadd.f32.v5f32(float %s, <5 x float> %a)
140 %b = call float @llvm.vector.reduce.fadd.f32.v5f32(float -0.0, <5 x float> %a)
Dvec-libcalls.ll12 declare <5 x float> @llvm.sin.v5f32(<5 x float>)
174 %r = call <5 x float> @llvm.sin.v5f32(<5 x float> %x)
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCallingConv.td41 CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,
82 CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,
212 CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,
DSIRegisterInfo.td719 def SGPR_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
724 def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
803 def VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>;
819 def AReg_160 : ARegClass<5, [v5i32, v5f32], (add AGPR_160)>;
DAMDGPUISelLowering.cpp86 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
87 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
206 setOperationAction(ISD::STORE, MVT::v5f32, Promote); in AMDGPUTargetLowering()
207 AddPromotedToType(ISD::STORE, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
335 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom); in AMDGPUTargetLowering()
344 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom); in AMDGPUTargetLowering()
465 MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32 in AMDGPUTargetLowering()
513 setOperationAction(ISD::SELECT, MVT::v5f32, Promote); in AMDGPUTargetLowering()
514 AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
DSIInstructions.td1031 f32, v5f32, Index, !cast<SubRegIndex>(sub#Index)
1034 f32, v5f32, Index, !cast<SubRegIndex>(sub#Index)
1188 def : BitConvert <v5i32, v5f32, SGPR_160>;
1189 def : BitConvert <v5f32, v5i32, SGPR_160>;
DSIISelLowering.cpp149 addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass); in SITargetLowering()
419 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom); in SITargetLowering()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h143 v5f32 = 88, // 5 x f32 enumerator
609 case v5f32: in getVectorElementType()
728 case v5f32: return 5; in getVectorNumElements()
909 case v5f32: return TypeSize::Fixed(160); in getSizeInBits()
1199 if (NumElements == 5) return MVT::v5f32; in getVectorVT()
/external/llvm-project/llvm/test/CodeGen/ARM/
Dvecreduce-fadd-legalization-strict.ll10 declare float @llvm.vector.reduce.fadd.f32.v5f32(float, <5 x float>)
171 %b = call float @llvm.vector.reduce.fadd.f32.v5f32(float %s, <5 x float> %a)
189 %b = call float @llvm.vector.reduce.fadd.f32.v5f32(float -0.0, <5 x float> %a)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallingConv.td124 CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,
DSIRegisterInfo.td539 def SGPR_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
544 def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
624 def VReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
DAMDGPUISelLowering.cpp82 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
83 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
182 setOperationAction(ISD::STORE, MVT::v5f32, Promote); in AMDGPUTargetLowering()
183 AddPromotedToType(ISD::STORE, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
283 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom); in AMDGPUTargetLowering()
292 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom); in AMDGPUTargetLowering()
399 MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32 in AMDGPUTargetLowering()
447 setOperationAction(ISD::SELECT, MVT::v5f32, Promote); in AMDGPUTargetLowering()
448 AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
DSIInstructions.td889 f32, v5f32, Index, !cast<SubRegIndex>(sub#Index)
892 f32, v5f32, Index, !cast<SubRegIndex>(sub#Index)
1044 def : BitConvert <v5i32, v5f32, SGPR_160>;
1045 def : BitConvert <v5f32, v5i32, SGPR_160>;
DSIISelLowering.cpp142 addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass); in SITargetLowering()
345 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom); in SITargetLowering()
/external/llvm-project/llvm/test/CodeGen/X86/
Dvec-libcalls.ll16 declare <5 x float> @llvm.sin.v5f32(<5 x float>)
157 %r = call <5 x float> @llvm.sin.v5f32(<5 x float> %x)
Doddshuffles.ll188 define void @v5f32(<4 x float> %a, <4 x float> %b, <5 x float>* %p) nounwind {
189 ; SSE2-LABEL: v5f32:
199 ; SSE42-LABEL: v5f32:
207 ; AVX-LABEL: v5f32:
215 ; XOP-LABEL: v5f32:
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td101 def v5f32 : ValueType<160, 74>; // 5 x f32 vector value
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp219 case MVT::v5f32: return VectorType::get(Type::getFloatTy(Context), 5); in getTypeForEVT()
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td116 def v5f32 : ValueType<160, 88>; // 5 x f32 vector value
/external/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp344 case MVT::v5f32: in getTypeForEVT()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp154 case MVT::v5f32: return "MVT::v5f32"; in getEnumName()