Home
last modified time | relevance | path

Searched refs:v64i1 (Results 1 – 25 of 57) sorted by relevance

123

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td188 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
191 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
194 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
197 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
242 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
245 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
300 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
303 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
314 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
325 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
[all …]
DX86CallingConv.td93 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
94 CCIfType<[v64i1], CCPromoteToType<i64>>,
172 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
173 CCIfType<[v64i1], CCPromoteToType<i64>>,
231 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
539 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
824 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrVecCompiler.td188 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
191 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
194 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
197 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
242 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
245 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
300 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
303 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
314 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
325 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
[all …]
DX86CallingConv.td93 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
94 CCIfType<[v64i1], CCPromoteToType<i64>>,
172 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
173 CCIfType<[v64i1], CCPromoteToType<i64>>,
231 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
545 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
831 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td28 def : Pat <(v64i1 (bitconvert (v16i32 HvxVR:$src1))),
29 (v64i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
31 def : Pat <(v64i1 (bitconvert (v32i16 HvxVR:$src1))),
32 (v64i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
34 def : Pat <(v64i1 (bitconvert (v64i8 HvxVR:$src1))),
35 (v64i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
37 def : Pat <(v16i32 (bitconvert (v64i1 HvxQR:$src1))),
38 (v16i32 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
40 def : Pat <(v32i16 (bitconvert (v64i1 HvxQR:$src1))),
41 (v32i16 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
DHexagonRegisterInfo.td322 [v64i1, v128i1, v64i1]>;
338 [v64i1, v128i1, v64i1]>;
340 [v32i1, v64i1, v32i1]>;
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h64 v64i1 = 18, // 64 x i1 enumerator
322 case v64i1: in getVectorElementType()
380 case v64i1: in getVectorNumElements()
470 case v64i1: in getSizeInBits()
598 if (NumElements == 64) return MVT::v64i1; in getVectorVT()
DValueTypes.td41 def v64i1 : ValueType<64 , 18>; // 64 x i1 vector value
/external/llvm-project/llvm/test/CodeGen/X86/
Dpr47299.ll7 declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64, i64)
9 declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i32(i32, i32)
108 %2 = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 0, i64 %0)
137 %2 = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i32(i32 0, i32 %0)
Davx512-regcall-Mask.ll6 ; Test regcall when receiving arguments of v64i1 type
95 ; Test regcall when passing arguments of v64i1 type
215 ; Test regcall when returning v64i1 type
231 ; Test regcall when processing result of v64i1 type
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h66 v64i1 = 20, // 64 x i1 enumerator
342 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 || in is64BitVector()
434 case v64i1: in getVectorElementType()
568 case v64i1: in getVectorNumElements()
737 case v64i1: in getSizeInBits()
929 if (NumElements == 64) return MVT::v64i1; in getVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h67 v64i1 = 21, // 64 x i1 enumerator
372 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 || in is64BitVector()
501 case v64i1: in getVectorElementType()
667 case v64i1: in getVectorNumElements()
866 case v64i1: in getSizeInBits()
1116 if (NumElements == 64) return MVT::v64i1; in getVectorVT()
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dreduce-xor.ll163 …estimated cost of 48 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
174 …estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
185 …estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
196 …estimated cost of 47 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
207 …estimated cost of 27 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
218 …stimated cost of 136 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
229 …stimated cost of 775 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
240 …stimated cost of 136 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
250 %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
288 declare i1 @llvm.vector.reduce.xor.v64i1(<64 x i1>)
Dreduce-or.ll163 …n estimated cost of 5 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
174 …n estimated cost of 5 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
185 …n estimated cost of 3 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
196 … estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
207 … estimated cost of 13 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
218 … estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
228 %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
266 declare i1 @llvm.vector.reduce.or.v64i1(<64 x i1>)
Dreduce-and.ll163 … estimated cost of 5 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
174 … estimated cost of 5 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
185 … estimated cost of 3 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
196 …estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
207 …estimated cost of 13 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
218 …estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
228 %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
266 declare i1 @llvm.vector.reduce.and.v64i1(<64 x i1>)
/external/llvm/lib/IR/
DValueTypes.cpp150 case MVT::v64i1: return "v64i1"; in getEVTString()
228 case MVT::v64i1: return VectorType::get(Type::getInt1Ty(Context), 64); in getTypeForEVT()
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dhvx-bitcast-v64i1.ll3 ; Test that LLVM does not assert and bitcast v64i1 to i64 is lowered
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td302 [v64i1, v128i1, v64i1]>;
304 [v32i1, v64i1, v32i1]>;
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp78 case MVT::v64i1: return "MVT::v64i1"; in getEnumName()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenDAGISel.inc7158 /* 15364*/ OPC_CheckChild1Type, MVT::v64i1,
7167 …// Src: (st VK64:{ *:[v64i1] }:$src, addr:{ *:[iPTR] }:$dst)<<P:Predicate_unindexedstore>><<P:Pred…
7168 // Dst: (KMOVQmk addr:{ *:[iPTR] }:$dst, VK64:{ *:[v64i1] }:$src)
8469 /* 18208*/ OPC_CheckChild4Type, MVT::v64i1,
8477 …[v64i8] }:$src, addr:{ *:[iPTR] }:$ptr, (undef:{ *:[iPTR] }), VK64WM:{ *:[v64i1] }:$mask)<<P:Predi…
8478 …// Dst: (VMOVDQU8Zmrk addr:{ *:[iPTR] }:$ptr, VK64WM:{ *:[v64i1] }:$mask, VR512:{ *:[v64i8] }:$src)
8486 …[v64i8] }:$src, addr:{ *:[iPTR] }:$dst, (undef:{ *:[iPTR] }), VK64WM:{ *:[v64i1] }:$mask)<<P:Predi…
8487 …// Dst: (VPCOMPRESSBZmrk addr:{ *:[iPTR] }:$dst, VK64WM:{ *:[v64i1] }:$mask, VR512:{ *:[v64i8] }:$…
23292 /* 47350*/ OPC_CheckType, MVT::v64i1,
23298 MVT::v64i1, 8/*#Ops*/, 0, 2, 5, 6, 7, 8, 9, 10,
[all …]
DX86GenCallingConv.inc531 if (LocVT == MVT::v64i1) {
849 if (LocVT == MVT::v64i1) {
1529 if (LocVT == MVT::v64i1) {
1918 if (LocVT == MVT::v64i1) {
2389 if (LocVT == MVT::v64i1) {
2776 if (LocVT == MVT::v64i1) {
3094 if (LocVT == MVT::v64i1) {
3667 if (LocVT == MVT::v64i1) {
3881 if (LocVT == MVT::v64i1) {
/external/llvm/lib/Target/X86/
DX86CallingConv.td51 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
328 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
601 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
DX86RegisterInfo.td517 def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}
525 def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td41 def v64i1 : ValueType<64 , 20>; // 64 x i1 vector value
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp165 case MVT::v64i1: return VectorType::get(Type::getInt1Ty(Context), 64); in getTypeForEVT()

123