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Searched refs:v8bf16 (Results 1 – 23 of 23) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AArch64/
Daarch64-bf16-ldst-intrinsics.ll88 …%vld1xN = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld1x2.v8bf16.p0bf16(bfloat* …
97 declare { <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld1x2.v8bf16.p0bf16(bfloat*) nounwind
124 …%vld1xN = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld1x3.v8bf16.p…
135 declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld1x3.v8bf16.p0bf16(bfloat*…
164 …at>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld1x4.v8bf16.p0bf16(bfloat* %pt…
177 declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld1x4.v8bf16.…
216 …%vld2 = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld2.v8bf16.p0v8bf16(<8 x bfloa…
225 declare { <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld2.v8bf16.p0v8bf16(<8 x bfloat>*) nounwi…
255 …%vld2_lane = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld2lane.v8bf16.p0i8(<8 x …
264 declare { <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld2lane.v8bf16.p0i8(<8 x bfloat>, <8 x bf…
[all …]
Daarch64-bf16-dotprod-intrinsics.ll20 …%vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %…
47 …%vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %…
74 …%vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %…
155 declare <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float>, <8 x bfloat>, <8 x bfloat>)
/external/llvm-project/llvm/test/CodeGen/ARM/
Dbf16-intrinsics-ld-st.ll84 …%vld1xN = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x2.v8bf16.p0bf16(bfloat* %pt…
120 …%vld1xN = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x3.v8bf16.p0bf…
162 …float>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x4.v8bf16.p0bf16(bfloat* %pt…
214 %vld2q_v = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2.v8bf16.p0i8(i8* %0, i32 2)
260 …%vld2q_lane_v = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2lane.v8bf16.p0i8(i8* %…
298 …%vld3q_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3.v8bf16.p0i8(…
356 …all { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3lane.v8bf16.p0i8(i8* %3, <8 x …
400 … bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4.v8bf16.p0i8(i8* %0, i32 2)
470 …oat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4lane.v8bf16.p0i8(i8* %4, <8 x …
511 …%vld2q_dup_v = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2dup.v8bf16.p0i8(i8* %0,…
[all …]
Darm-bf16-dotprod-intrinsics.ll20 …%vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %a, <…
47 …%vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %a, <…
74 …%vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %a, <…
167 declare <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float>, <8 x bfloat>, <8 x bfloat>)
/external/llvm-project/llvm/lib/Target/ARM/
DARMCallingConv.td34 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
60 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
75 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
95 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
112 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
169 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
187 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
214 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
237 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
DARMInstrNEON.td1066 def : Pat<(vector_insert (v8bf16 QPR:$src),
6388 defm : ExtractEltOddF16VMOVH<v4bf16, v8bf16>;
6392 defm : ExtractEltEvenF16<v4bf16, v8bf16>;
6401 def : Pat<(extractelt (v8bf16 QPR:$src), imm_odd:$lane),
6519 defm : InsertEltF16<bf16, v4bf16, v8bf16>;
6643 def : Pat<(v8bf16 (ARMvduplane (v8bf16 QPR:$src), imm:$lane)),
6644 (v8bf16 (VDUPLN16q (v4bf16 (EXTRACT_SUBREG QPR:$src,
6651 def : Pat<(v8bf16 (ARMvdup (bf16 HPR:$src))),
6652 (v8bf16 (VDUPLN16q (INSERT_SUBREG (v4bf16 (IMPLICIT_DEF)),
7412 def : Pat<(v8i16 (bitconvert (v8bf16 QPR:$src))), (v8i16 QPR:$src)>;
[all …]
DARMCallingConv.cpp222 case MVT::v8bf16: in CC_ARM_AAPCS_Custom_Aggregate()
DARMRegisterInfo.td449 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16, v8bf16], 128,
DARMISelDAGToDAG.cpp2089 case MVT::v8bf16: in SelectVLD()
2234 case MVT::v8bf16: in SelectVST()
2402 case MVT::v8bf16: in SelectVLDSTLane()
2933 case MVT::v8bf16: in SelectVLDDup()
DARMISelLowering.cpp809 addQRTypeForNEON(MVT::v8bf16); in ARMTargetLowering()
4352 RegVT == MVT::v8bf16) in LowerFormalArguments()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp3546 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) { in Select()
3573 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) { in Select()
3600 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) { in Select()
3627 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) { in Select()
3654 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) { in Select()
3681 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) { in Select()
3708 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) { in Select()
3735 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) { in Select()
3762 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) { in Select()
3784 VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) { in Select()
[all …]
DAArch64CallingConvention.td35 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
111 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
119 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
136 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
155 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
232 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
248 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
269 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
291 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
DAArch64InstrInfo.td818 (v8bf16 (insert_subvector undef,
2327 defm : VecROLoadPat<ro128, v8bf16, LDRQroW, LDRQroX>;
2488 def : Pat<(v8bf16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
3004 defm : VecROStorePat<ro128, v8bf16, FPR128, STRQroW, STRQroX>;
3130 def : Pat<(store (v8bf16 FPR128:$Rt),
3275 def : Pat<(store (v8bf16 FPR128:$Rt),
3986 def : Pat<(v8bf16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
3987 def : Pat<(v8bf16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
4861 defm : ExtPat<v4bf16, v8bf16, 4>;
4991 def : Pat<(v8bf16 (AArch64dup (bf16 FPR16:$Rn))),
[all …]
DAArch64RegisterInfo.td449 v8f16, v8bf16],
456 v8bf16],
DAArch64InstrFormats.td7852 def v8bf16 : BaseSIMDThreeSameVectorBFDot<1, U, asm, ".4s", ".8h", V128,
7853 v4f32, v8bf16>;
7882 def v8bf16 : BaseSIMDThreeSameVectorBF16DotI<1, U, asm, ".4s", ".8h",
7883 ".2h", V128, v4f32, v8bf16>;
7889 (v8bf16 V128:$Rn),
7890 (v8bf16 V128:$Rm)))]> {
7900 (v8bf16 V128:$Rn),
7901 (v8bf16
7902 (AArch64duplane16 (v8bf16 V128_lo:$Rm),
7927 (v8bf16 V128:$Rn),
[all …]
DAArch64ISelLowering.cpp253 addQRTypeForNEON(MVT::v8bf16); in AArch64TargetLowering()
9691 VT == MVT::v8f16 || VT == MVT::v8bf16) in LowerINSERT_VECTOR_ELT()
9726 VT == MVT::v8f16 || VT == MVT::v8bf16) in LowerEXTRACT_VECTOR_ELT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h134 v8bf16 = 79, // 8 x bf16 enumerator
384 SimpleTy == MVT::v8f16 || SimpleTy == MVT::v8bf16 || in is128BitVector()
597 case v8bf16: in getVectorElementType()
715 case v8bf16: in getVectorNumElements()
897 case v8bf16: in getSizeInBits()
1188 if (NumElements == 8) return MVT::v8bf16; in getVectorVT()
/external/llvm-project/llvm/test/Bitcode/
Daarch64-bf16-upgrade.ll24 …; CHECK-NEXT: %vbfdot1.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %r, …
70 ; CHECK: declare <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float>, <8 x bfloat>, <8 x …
Darm-bf16-upgrade.ll25 …; CHECK-NEXT: %vbfdot1.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x…
70 ; CHECK: declare <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float>, <8 x bfloat>, <8 x bflo…
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td107 def v8bf16 : ValueType<128, 79>; // 8 x bf16 vector value
/external/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp326 case MVT::v8bf16: in getTypeForEVT()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp145 case MVT::v8bf16: return "MVT::v8bf16"; in getEnumName()
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsics.td310 def llvm_v8bf16_ty : LLVMType<v8bf16>; // 8 x bfloat (__bf16)