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Searched refs:v8i32 (Results 1 – 25 of 303) sorted by relevance

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/external/llvm-project/llvm/test/Verifier/
Dvp-intrinsics.ll4 %r0 = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
5 %r1 = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
6 %r2 = call <8 x i32> @llvm.vp.mul.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
7 %r3 = call <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
8 %r4 = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
9 %r5 = call <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
10 %r6 = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
11 %r7 = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
12 %r8 = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
13 %r9 = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
[all …]
/external/llvm-project/llvm/test/Transforms/InstSimplify/ConstProp/
Dvecreduce.ll5 declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %a)
7 declare i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> %a)
9 declare i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %a)
11 declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %a)
13 declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %a)
15 declare i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %a)
17 declare i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %a)
19 declare i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %a)
21 declare i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %a)
28 %x = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> zeroinitializer)
[all …]
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
154 { ISD::SHL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
155 { ISD::SRL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
156 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost()
197 { ISD::SHL, MVT::v8i32, 2 }, in getArithmeticInstrCost()
198 { ISD::SRL, MVT::v8i32, 4 }, in getArithmeticInstrCost()
199 { ISD::SRA, MVT::v8i32, 4 }, in getArithmeticInstrCost()
226 { ISD::SDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
230 { ISD::UDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dcanonicalize-vector-extract.ll7 declare <10 x i32> @llvm.experimental.vector.extract.v10i32.v8i32(<8 x i32> %vec, i64 %idx)
9 declare <3 x i32> @llvm.experimental.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 %idx)
11 declare <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 %idx)
12 declare <8 x i32> @llvm.experimental.vector.extract.v8i32.v8i32(<8 x i32> %vec, i64 %idx)
23 %1 = call <8 x i32> @llvm.experimental.vector.extract.v8i32.v8i32(<8 x i32> %vec, i64 0)
72 %1 = call <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 0)
81 %1 = call <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 4)
90 %1 = call <3 x i32> @llvm.experimental.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 0)
99 %1 = call <3 x i32> @llvm.experimental.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 3)
113 %1 = call <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 1)
[all …]
Dcanonicalize-vector-insert.ll7 declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i…
8 declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec, i…
9 declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec, i…
10 declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v8i32(<8 x i32> %vec, <8 x i32> %subvec, i…
23 …%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v8i32(<8 x i32> %vec, <8 x i32> %subvec…
37 …%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec…
47 …%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec…
57 …%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec…
67 …%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec…
77 …%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp392 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
393 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
394 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
395 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
422 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. in getArithmeticInstrCost()
423 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
426 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. in getArithmeticInstrCost()
427 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
436 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) in getArithmeticInstrCost()
438 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) in getArithmeticInstrCost()
[all …]
DX86InstrVecCompiler.td71 defm : subvector_subreg_lowering<VR128, v4i32, VR256, v8i32, sub_xmm>;
93 defm : subvector_subreg_lowering<VR256, v8i32, VR512, v16i32, sub_ymm>;
115 defm : subvec_zero_lowering<"APD", VR128, v4f64, v2f64, v8i32, sub_xmm>;
116 defm : subvec_zero_lowering<"APS", VR128, v8f32, v4f32, v8i32, sub_xmm>;
117 defm : subvec_zero_lowering<"DQA", VR128, v4i64, v2i64, v8i32, sub_xmm>;
118 defm : subvec_zero_lowering<"DQA", VR128, v8i32, v4i32, v8i32, sub_xmm>;
119 defm : subvec_zero_lowering<"DQA", VR128, v16i16, v8i16, v8i32, sub_xmm>;
120 defm : subvec_zero_lowering<"DQA", VR128, v32i8, v16i8, v8i32, sub_xmm>;
124 defm : subvec_zero_lowering<"APDZ128", VR128X, v4f64, v2f64, v8i32, sub_xmm>;
125 defm : subvec_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, v8i32, sub_xmm>;
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp345 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence in getArithmeticInstrCost()
346 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
347 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence in getArithmeticInstrCost()
348 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
367 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. in getArithmeticInstrCost()
368 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
371 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. in getArithmeticInstrCost()
372 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
436 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
437 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
[all …]
DX86InstrVecCompiler.td71 defm : subvector_subreg_lowering<VR128, v4i32, VR256, v8i32, sub_xmm>;
93 defm : subvector_subreg_lowering<VR256, v8i32, VR512, v16i32, sub_ymm>;
115 defm : subvec_zero_lowering<"APD", VR128, v4f64, v2f64, v8i32, sub_xmm>;
116 defm : subvec_zero_lowering<"APS", VR128, v8f32, v4f32, v8i32, sub_xmm>;
117 defm : subvec_zero_lowering<"DQA", VR128, v4i64, v2i64, v8i32, sub_xmm>;
118 defm : subvec_zero_lowering<"DQA", VR128, v8i32, v4i32, v8i32, sub_xmm>;
119 defm : subvec_zero_lowering<"DQA", VR128, v16i16, v8i16, v8i32, sub_xmm>;
120 defm : subvec_zero_lowering<"DQA", VR128, v32i8, v16i8, v8i32, sub_xmm>;
124 defm : subvec_zero_lowering<"APDZ128", VR128X, v4f64, v2f64, v8i32, sub_xmm>;
125 defm : subvec_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, v8i32, sub_xmm>;
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dpr45067.ll17 …%tmp = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> <i32* @global, i32* @global, i3…
18 call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %tmp, <8 x i32>* %x, i32 4, <8 x i1> %y)
22 declare <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*>, i32, <8 x i1>, <8 x i32>)
23 declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)
Dpr28515.ll10 …%wide.masked.load = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* bitcast (i32* getele…
14 declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) #0
/external/llvm-project/llvm/test/Analysis/CostModel/AArch64/
Dmin-max.ll102 ; COST-LABEL: umin.v8i32
103 …n estimated cost of 2 for instruction: %res = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %v0, <8 …
105 ; CODE-LABEL: umin.v8i32
111 declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>)
112 define <8 x i32> @umin.v8i32(<8 x i32> %v0, <8 x i32> %v1) {
113 %res = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %v0, <8 x i32> %v1)
230 ; COST-LABEL: smin.v8i32
231 …n estimated cost of 2 for instruction: %res = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %v0, <8 …
233 ; CODE-LABEL: smin.v8i32
239 declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>)
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.SI.gather4.ll86 …%r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> unde…
153 …%r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> unde…
179 …%r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef…
205 …%r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef…
218 …%r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> un…
272 …%r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> unde…
298 …%r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef…
324 …%r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef…
337 …%r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> un…
378 …%r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef…
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenDAGISel.inc257 /* 421*/ OPC_CheckChild1Type, MVT::v8i32,
269 …// Src: (st VR256:{ *:[v8i32] }:$src, addr:{ *:[iPTR] }:$dst)<<P:Predicate_unindexedstore>><<P:Pre…
270 // Dst: (VMOVNTDQYmr addr:{ *:[iPTR] }:$dst, VR256:{ *:[v8i32] }:$src)
277 …// Src: (st VR256X:{ *:[v8i32] }:$src, addr:{ *:[iPTR] }:$dst)<<P:Predicate_unindexedstore>><<P:Pr…
278 // Dst: (VMOVNTDQZ256mr addr:{ *:[iPTR] }:$dst, VR256X:{ *:[v8i32] }:$src)
5375 /* 11548*/ OPC_CheckChild0Type, MVT::v8i32,
5393 …// Src: (st (extract_subvector:{ *:[v4i32] } VR256:{ *:[v8i32] }:$src1, (imm:{ *:[iPTR] }))<<P:Pre…
5394 …// Dst: (VEXTRACTF128mr addr:{ *:[iPTR] }:$dst, VR256:{ *:[v8i32] }:$src1, (EXTRACT_get_vextract12…
5402 …// Src: (st (extract_subvector:{ *:[v4i32] } VR256:{ *:[v8i32] }:$src1, (imm:{ *:[iPTR] }))<<P:Pre…
5403 …// Dst: (VEXTRACTI128mr addr:{ *:[iPTR] }:$dst, VR256:{ *:[v8i32] }:$src1, (EXTRACT_get_vextract12…
[all …]
/external/llvm-project/mlir/test/Target/
Dllvmir-intrinsics.mlir133 // CHECK: call <8 x i32> @llvm.bitreverse.v8i32
142 // CHECK: call <8 x i32> @llvm.ctpop.v8i32
169 // CHECK: call <8 x i32> @llvm.smax.v8i32
178 // CHECK: call <8 x i32> @llvm.smin.v8i32
185 // CHECK: call i32 @llvm.vector.reduce.add.v8i32
187 // CHECK: call i32 @llvm.vector.reduce.and.v8i32
193 // CHECK: call i32 @llvm.vector.reduce.mul.v8i32
195 // CHECK: call i32 @llvm.vector.reduce.or.v8i32
197 // CHECK: call i32 @llvm.vector.reduce.smax.v8i32
199 // CHECK: call i32 @llvm.vector.reduce.smin.v8i32
[all …]
/external/llvm/test/CodeGen/X86/
Dpr28515.ll10 …%wide.masked.load = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* bitcast (i32* getele…
14 declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) #0
/external/llvm-project/llvm/test/Instrumentation/HeapProfiler/
Dmasked-load-store.ll14 @v8i32 = global <8 x i32>* zeroinitializer, align 8
19 declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>) argmemonly noun…
40 define void @store.v8i32.10010110(<8 x i32> %arg) {
41 ; ALL-LABEL: @store.v8i32.10010110
42 %p = load <8 x i32>*, <8 x i32>** @v8i32, align 8
56 ; STORE: tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x…
57 …tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> <i1…
136 declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) argmemonly …
139 define <8 x i32> @load.v8i32.11100001(<8 x i32> %arg) {
140 ; ALL-LABEL: @load.v8i32.11100001
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h90 v8i32 = 41, // 8 x i32 enumerator
259 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); in is256BitVector()
345 case v8i32: in getVectorElementType()
398 case v8i32: in getVectorNumElements()
492 case v8i32: in getSizeInBits()
627 if (NumElements == 8) return MVT::v8i32; in getVectorVT()
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dbswap.ll16 declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)
76 …nd an estimated cost of 14 for instruction: %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)
80 …und an estimated cost of 2 for instruction: %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)
84 …und an estimated cost of 4 for instruction: %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)
88 …und an estimated cost of 1 for instruction: %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)
91 %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)
/external/llvm-project/llvm/test/Instrumentation/AddressSanitizer/
Dasan-masked-load-store.ll22 @v8i32 = global <8 x i32>* zeroinitializer, align 8
27 declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>) argmemonly noun…
48 define void @store.v8i32.10010110(<8 x i32> %arg) sanitize_address {
49 ; ALL-LABEL: @store.v8i32.10010110
50 %p = load <8 x i32>*, <8 x i32>** @v8i32, align 8
64 ; STORE: tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x…
65 …tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> <i1…
158 declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) argmemonly …
161 define <8 x i32> @load.v8i32.11100001(<8 x i32> %arg) sanitize_address {
162 ; ALL-LABEL: @load.v8i32.11100001
[all …]
/external/llvm-project/llvm/test/Transforms/LoopVectorize/X86/
Dtail_loop_folding.ll24 ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32…
28 ; CHECK-NEXT: [[WIDE_MASKED_LOAD1:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i3…
33 ; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> [[TMP8]], <8 x i32>* [[TMP11]…
95 ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32…
99 ; CHECK-NEXT: [[WIDE_MASKED_LOAD1:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i3…
104 ; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> [[TMP8]], <8 x i32>* [[TMP11]…
184 ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32…
188 ; CHECK-NEXT: [[WIDE_MASKED_LOAD3:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i3…
196 ; CHECK-NEXT: [[TMP15:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP13]])
/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Disel-widen-memop.ll17 …%v5 = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* nonnull undef, i32 4, <8 x i1> %v4…
29 declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32 immarg, <8 x i1>, <8 x i32>) #1
Disel-widen-truncate-op.ll18 …%v5 = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* nonnull undef, i32 4, <8 x i1> %v4…
30 declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32 immarg, <8 x i1>, <8 x i32>) #1
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp193 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
201 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
202 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
203 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
204 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
447 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 }, in getCmpSelInstrCost()
/external/llvm-project/llvm/test/Transforms/StructurizeCFG/
Drebuild-ssa-infinite-loop.ll24 …%tmp8 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %tmp5, <8 x i32> unde…
49 declare <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32>, <8 x i32>, i32, i1, i1, i1…

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