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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dsrem.i64.ll31 ; CHECK-NEXT: v_sub_i32_e32 v9, vcc, 0, v5
41 ; CHECK-NEXT: v_mul_lo_u32 v12, v9, v8
42 ; CHECK-NEXT: v_mul_hi_u32 v14, v9, v4
43 ; CHECK-NEXT: v_mul_lo_u32 v13, v9, v4
71 ; CHECK-NEXT: v_mul_lo_u32 v13, v9, v12
72 ; CHECK-NEXT: v_mul_lo_u32 v14, v9, v4
73 ; CHECK-NEXT: v_mul_hi_u32 v9, v9, v4
77 ; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v10, v9
79 ; CHECK-NEXT: v_mul_lo_u32 v13, v4, v9
85 ; CHECK-NEXT: v_mul_lo_u32 v11, v12, v9
[all …]
Durem.i64.ll32 ; CHECK-NEXT: v_mul_lo_u32 v9, v6, v4
36 ; CHECK-NEXT: v_mul_lo_u32 v10, v5, v9
37 ; CHECK-NEXT: v_mul_hi_u32 v12, v4, v9
38 ; CHECK-NEXT: v_mul_hi_u32 v9, v5, v9
46 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v13, v9
50 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v14
54 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
58 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v9
59 ; CHECK-NEXT: v_addc_u32_e64 v9, s[4:5], v5, v8, vcc
64 ; CHECK-NEXT: v_mul_lo_u32 v6, v6, v9
[all …]
Dsdiv.i64.ll33 ; CHECK-NEXT: v_mul_f32_e32 v9, 0x2f800000, v6
34 ; CHECK-NEXT: v_trunc_f32_e32 v9, v9
35 ; CHECK-NEXT: v_mac_f32_e32 v6, 0xcf800000, v9
37 ; CHECK-NEXT: v_cvt_u32_f32_e32 v9, v9
41 ; CHECK-NEXT: v_mul_lo_u32 v13, v10, v9
47 ; CHECK-NEXT: v_mul_lo_u32 v13, v9, v14
50 ; CHECK-NEXT: v_mul_hi_u32 v14, v9, v14
55 ; CHECK-NEXT: v_mul_lo_u32 v16, v9, v12
58 ; CHECK-NEXT: v_mul_hi_u32 v12, v9, v12
69 ; CHECK-NEXT: v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
[all …]
Dudiv.i64.ll32 ; CHECK-NEXT: v_mul_lo_u32 v9, v6, v4
36 ; CHECK-NEXT: v_mul_lo_u32 v10, v5, v9
37 ; CHECK-NEXT: v_mul_hi_u32 v12, v4, v9
38 ; CHECK-NEXT: v_mul_hi_u32 v9, v5, v9
46 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v13, v9
50 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v14
54 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
58 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v9
59 ; CHECK-NEXT: v_addc_u32_e64 v9, s[4:5], v5, v8, vcc
64 ; CHECK-NEXT: v_mul_lo_u32 v6, v6, v9
[all …]
/external/libxaac/decoder/armv8/
Dixheaacd_inv_dit_fft_8pt.s59 SQADD v9.2s, v1.2s, v5.2s //a00_v = vqadd_s32(y0_2,y8_10);
69 SQADD v3.2s, v9.2s, v11.2s //x0_8 = vqadd_s32(a00_v,a10_v);
72 SQSUB v4.2s, v9.2s, v11.2s //x4_12 = vqsub_s32(a00_v,a10_v);
75 SQADD v9.2s, v1.2s, v6.2s //x6_14 = vqadd_s32(a0_v,a1_v);
121 UZP1 v1.2s, v9.2s, v13.2s //x6_7
122 SQADD v6.2s, v9.2s, v13.2s //tempr = vqadd_s32(x6_14,x7_15);
123 SQSUB v14.2s, v9.2s, v13.2s //tempi = vqsub_s32(x6_14,x7_15);
125 SMULL v9.2d, v6.2s, v0.2s
128 SSHR v9.2d, v9.2d, #32
131 SHL v9.4s, v9.4s, #1
[all …]
Dixheaacd_pre_twiddle.s158 LD2 {v8.h, v9.h}[0], [x3], x6
159 LD2 {v8.h, v9.h}[1], [x3], x6
160 LD2 {v8.h, v9.h}[2], [x3], x6
161 LD2 {v8.h, v9.h}[3], [x3], x6
164 rev64 v11.4h, v9.4h
181 uMULL v30.4s, v2.4h, v9.4h
182 uMULL v28.4s, v4.4h, v9.4h
191 sMLAL v30.4s, v3.4h, v9.4h
192 sMLAL v28.4s, v5.4h, v9.4h
211 LD2 {v8.h, v9.h}[0], [x3], x6
[all …]
Dixheaacd_post_twiddle.s142 LD2 {v8.h, v9.h}[0], [x2], x6
143 LD2 {v8.h, v9.h}[1], [x2], x6
144 LD2 {v8.h, v9.h}[2], [x2], x6
145 LD2 {v8.h, v9.h}[3], [x2], x6
148 rev64 v13.4h, v9.4h
165 uMULL v22.4s, v6.4h, v9.4h
166 uMULL v20.4s, v4.4h, v9.4h
195 sMLAL v22.4s, v7.4h, v9.4h
196 sMLAL v20.4s, v5.4h, v9.4h
200 LD2 {v8.h, v9.h}[0], [x2], x6
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dbypass-div.ll28 ; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, 0, v5, vcc
39 ; GFX9-NEXT: v_mul_lo_u32 v10, v9, v6
62 ; GFX9-NEXT: v_mul_lo_u32 v9, v9, v6
65 ; GFX9-NEXT: v_add3_u32 v9, v13, v12, v9
66 ; GFX9-NEXT: v_mul_lo_u32 v12, v6, v9
68 ; GFX9-NEXT: v_mul_hi_u32 v14, v6, v9
74 ; GFX9-NEXT: v_mul_hi_u32 v8, v10, v9
75 ; GFX9-NEXT: v_mul_lo_u32 v9, v10, v9
78 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v12, v9
81 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v9
[all …]
/external/llvm-project/llvm/test/MC/AMDGPU/
Dvop3-errs.s16 v_mqsad_pk_u16_u8 v[0:1], v[1:2], v9, v[4:5]
19 v_mqsad_pk_u16_u8 v[1:2], v[1:2], v9, v[4:5]
22 v_mqsad_pk_u16_u8 v[2:3], v[1:2], v9, v[4:5]
25 v_mqsad_pk_u16_u8 v[3:4], v[0:1], v9, v[4:5]
28 v_mqsad_pk_u16_u8 v[4:5], v[1:2], v9, v[4:5]
31 v_mqsad_pk_u16_u8 v[5:6], v[1:2], v9, v[4:5]
34 v_mqsad_pk_u16_u8 v[8:9], v[1:2], v9, v[4:5]
37 v_mqsad_pk_u16_u8 v[9:10], v[1:2], v9, v[4:5]
/external/llvm/test/MC/AArch64/
Dnoneon-diagnostics.s6 fmla v9.2s, v9.2s, v0.2s
19 fmls v9.2s, v9.2s, v0.2s
34 fmls.2s v9, v9, v0
Dneon-simd-misc.s12 rev64 v1.8b, v9.8b
26 rev32 v0.4h, v9.4h
45 saddlp v9.4s, v1.8h
63 uaddlp v9.4s, v1.8h
81 sadalp v9.4s, v1.8h
99 uadalp v9.4s, v1.8h
119 suqadd v1.8b, v9.8b
139 usqadd v1.8b, v9.8b
159 sqabs v1.8b, v9.8b
179 sqneg v1.8b, v9.8b
[all …]
Darm64-simd-ldst.s12 ld1.8b {v7, v8, v9, v10}, [x4]
103 ; CHECK: ld1.8b { v7, v8, v9, v10 }, [x4] ; encoding: [0x87,0x20,0x40,0x0c]
231 ld3.8b {v9, v10, v11}, [x9]
237 ld3.2d {v7, v8, v9}, [x9]
252 st3.4s {v7, v8, v9}, [x29]
264 ; CHECK: ld3.8b { v9, v10, v11 }, [x9] ; encoding: [0x29,0x41,0x40,0x0c]
270 ; CHECK: ld3.2d { v7, v8, v9 }, [x9] ; encoding: [0x27,0x4d,0x40,0x4c]
285 ; CHECK: st3.4s { v7, v8, v9 }, [x29] ; encoding: [0xa7,0x4b,0x00,0x4c]
1032 ld4r.4h {v6, v7, v8, v9}, [x2], #8
1059 ; CHECK: ld4r.4h { v6, v7, v8, v9 }, [x2], #8 ; encoding: [0x46,0xe4,0xff,0x0d]
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Dnoneon-diagnostics.s6 fmla v9.2s, v9.2s, v0.2s
19 fmls v9.2s, v9.2s, v0.2s
34 fmls.2s v9, v9, v0
Dneon-simd-misc.s12 rev64 v1.8b, v9.8b
26 rev32 v0.4h, v9.4h
45 saddlp v9.4s, v1.8h
63 uaddlp v9.4s, v1.8h
81 sadalp v9.4s, v1.8h
99 uadalp v9.4s, v1.8h
119 suqadd v1.8b, v9.8b
139 usqadd v1.8b, v9.8b
159 sqabs v1.8b, v9.8b
179 sqneg v1.8b, v9.8b
[all …]
Darm64-simd-ldst.s12 ld1.8b {v7, v8, v9, v10}, [x4]
103 ; CHECK: ld1.8b { v7, v8, v9, v10 }, [x4] ; encoding: [0x87,0x20,0x40,0x0c]
231 ld3.8b {v9, v10, v11}, [x9]
237 ld3.2d {v7, v8, v9}, [x9]
252 st3.4s {v7, v8, v9}, [x29]
264 ; CHECK: ld3.8b { v9, v10, v11 }, [x9] ; encoding: [0x29,0x41,0x40,0x0c]
270 ; CHECK: ld3.2d { v7, v8, v9 }, [x9] ; encoding: [0x27,0x4d,0x40,0x4c]
285 ; CHECK: st3.4s { v7, v8, v9 }, [x29] ; encoding: [0xa7,0x4b,0x00,0x4c]
1032 ld4r.4h {v6, v7, v8, v9}, [x2], #8
1059 ; CHECK: ld4r.4h { v6, v7, v8, v9 }, [x2], #8 ; encoding: [0x46,0xe4,0xff,0x0d]
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dswp-disable-Os.ll23 %v9 = phi i8* [ %v5, %b1 ], [ %v91, %b2 ]
26 %v12 = load i8, i8* %v9, align 1, !tbaa !0
30 %v16 = getelementptr inbounds i8, i8* %v9, i32 1
35 %v21 = getelementptr inbounds i8, i8* %v9, i32 2
40 %v26 = getelementptr inbounds i8, i8* %v9, i32 3
45 %v31 = getelementptr inbounds i8, i8* %v9, i32 4
50 %v36 = getelementptr inbounds i8, i8* %v9, i32 5
55 %v41 = getelementptr inbounds i8, i8* %v9, i32 6
60 %v46 = getelementptr inbounds i8, i8* %v9, i32 7
65 %v51 = getelementptr inbounds i8, i8* %v9, i32 8
[all …]
/external/XNNPACK/src/qs8-igemm/
D4x16c4-aarch64-neondot-cortex-a55.S29 # B x5 v8 v9 v10 v11
126 INS v9.d[1], x14
133 SDOT v20.4s, v9.16b, v0.4b[0]
135 SDOT v21.4s, v9.16b, v1.4b[0]
137 SDOT v22.4s, v9.16b, v2.4b[0]
139 SDOT v23.4s, v9.16b, v3.4b[0]
166 INS v9.d[1], x14
172 SDOT v20.4s, v9.16b, v0.4b[1]
174 SDOT v21.4s, v9.16b, v1.4b[1]
176 SDOT v22.4s, v9.16b, v2.4b[1]
[all …]
/external/XNNPACK/src/qs8-gemm/
D4x16c4-aarch64-neondot-cortex-a55.S27 # B x5 v8 v9 v10 v11
105 INS v9.d[1], x14
112 SDOT v20.4s, v9.16b, v0.4b[0]
114 SDOT v21.4s, v9.16b, v1.4b[0]
116 SDOT v22.4s, v9.16b, v2.4b[0]
118 SDOT v23.4s, v9.16b, v3.4b[0]
145 INS v9.d[1], x14
151 SDOT v20.4s, v9.16b, v0.4b[1]
153 SDOT v21.4s, v9.16b, v1.4b[1]
155 SDOT v22.4s, v9.16b, v2.4b[1]
[all …]
/external/libavc/encoder/armv8/
Dih264e_evaluate_intra16x16_modes_av8.s164 ld1 {v9.16b}, [x1]
168 dup v20.8b, v9.b[15] ///HORIZONTAL VALUE ROW=0//
169 dup v21.8b, v9.b[15] ///HORIZONTAL VALUE ROW=0//
189 dup v20.8b, v9.b[14] ///HORIZONTAL VALUE ROW=1//
190 dup v21.8b, v9.b[14]
206 dup v20.8b, v9.b[13] ///HORIZONTAL VALUE ROW=2//
207 dup v21.8b, v9.b[13]
222 dup v20.8b, v9.b[12] ///HORIZONTAL VALUE ROW=3//
223 dup v21.8b, v9.b[12]
239 dup v20.8b, v9.b[11] ///HORIZONTAL VALUE ROW=0//
[all …]
/external/capstone/suite/MC/AArch64/
Dneon-simd-misc.s.cs5 0x21,0x09,0x20,0x0e = rev64 v1.8b, v9.8b
11 0x20,0x09,0x60,0x2e = rev32 v0.4h, v9.4h
16 0x29,0x28,0x60,0x4e = saddlp v9.4s, v1.8h
22 0x29,0x28,0x60,0x6e = uaddlp v9.4s, v1.8h
28 0x29,0x68,0x60,0x4e = sadalp v9.4s, v1.8h
34 0x29,0x68,0x60,0x6e = uadalp v9.4s, v1.8h
42 0x21,0x39,0x20,0x0e = suqadd v1.8b, v9.8b
49 0x21,0x39,0x20,0x2e = usqadd v1.8b, v9.8b
56 0x21,0x79,0x20,0x0e = sqabs v1.8b, v9.8b
63 0x21,0x79,0x20,0x2e = sqneg v1.8b, v9.8b
[all …]
Dneon-compare-instructions.s.cs7 0xe9,0x8c,0xa8,0x6e = cmeq v9.4s, v7.4s, v8.4s
14 0xe9,0x3c,0xa8,0x6e = cmhs v9.4s, v7.4s, v8.4s
21 0xe9,0x3c,0xa8,0x6e = cmhs v9.4s, v7.4s, v8.4s
28 0xe9,0x3c,0xa8,0x4e = cmge v9.4s, v7.4s, v8.4s
35 0xe9,0x3c,0xa8,0x4e = cmge v9.4s, v7.4s, v8.4s
42 0xe9,0x34,0xa8,0x6e = cmhi v9.4s, v7.4s, v8.4s
49 0xe9,0x34,0xa8,0x6e = cmhi v9.4s, v7.4s, v8.4s
56 0xe9,0x34,0xa8,0x4e = cmgt v9.4s, v7.4s, v8.4s
63 0xe9,0x34,0xa8,0x4e = cmgt v9.4s, v7.4s, v8.4s
70 0xe9,0x8c,0xa8,0x4e = cmtst v9.4s, v7.4s, v8.4s
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dgfx10_mimg.txt75 # GFX10: image_atomic_cmpswap v[16:17], [v8, v9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm glc …
78 # GFX10: image_atomic_add v16, [v8, v9, v10], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm glc ; en…
81 # GFX10: image_atomic_sub v16, [v8, v9, v10], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm glc ; …
84 # GFX10: image_atomic_smin v16, [v8, v9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc ; …
87 # GFX10: image_atomic_umin v16, [v8, v9, v10], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm g…
90 # GFX10: image_atomic_smax v16, [v8, v9, v10], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm gl…
93 # GFX10: image_atomic_umax v16, [v8, v9, v10, v11], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARR…
118 # GFX10: image_sample_cl v[16:17], [v8, v9, v10], s[96:103], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_2D d1…
121 # GFX10: image_sample_d v[16:19], [v8, v9, v10], s[96:103], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D ; e…
124 # GFX10: image_sample_d_cl v[16:19], [v8, v9, v10, v11, v12, v13, v14], s[20:27], s[4:7] dmask:0xf …
[all …]
/external/llvm-project/mlir/integration_test/Dialect/Vector/CPU/
Dtest-reductions-i64.mlir27 %v9 = vector.insert %i10, %v8[9] : i64 into vector<10xi64>
28 vector.print %v9 : vector<10xi64>
36 %0 = vector.reduction "add", %v9 : vector<10xi64> into i64
39 %1 = vector.reduction "mul", %v9 : vector<10xi64> into i64
42 %2 = vector.reduction "min", %v9 : vector<10xi64> into i64
45 %3 = vector.reduction "max", %v9 : vector<10xi64> into i64
48 %4 = vector.reduction "and", %v9 : vector<10xi64> into i64
51 %5 = vector.reduction "or", %v9 : vector<10xi64> into i64
54 %6 = vector.reduction "xor", %v9 : vector<10xi64> into i64
Dtest-reductions-i32.mlir27 %v9 = vector.insert %i10, %v8[9] : i32 into vector<10xi32>
28 vector.print %v9 : vector<10xi32>
36 %0 = vector.reduction "add", %v9 : vector<10xi32> into i32
39 %1 = vector.reduction "mul", %v9 : vector<10xi32> into i32
42 %2 = vector.reduction "min", %v9 : vector<10xi32> into i32
45 %3 = vector.reduction "max", %v9 : vector<10xi32> into i32
48 %4 = vector.reduction "and", %v9 : vector<10xi32> into i32
51 %5 = vector.reduction "or", %v9 : vector<10xi32> into i32
54 %6 = vector.reduction "xor", %v9 : vector<10xi32> into i32
/external/libhevc/common/arm64/
Dihevc_itrans_recon_32x32.s211 ld1 {v9.4h},[x0],x6
218 smlal v24.4s, v9.4h, v0.h[3] //// y1 * cos1 + y3 * cos3(part of b0)
219 smlal v26.4s, v9.4h, v2.h[1] //// y1 * cos3 - y3 * sin1(part of b1)
220 smlal v28.4s, v9.4h, v3.h[3] //// y1 * sin3 - y3 * cos1(part of b2)
221 smlal v30.4s, v9.4h, v5.h[1] //// y1 * sin1 - y3 * sin3(part of b3)
280 ld1 {v9.4h},[x0],x6
288 smlal v24.4s, v9.4h, v2.h[3] //// y1 * cos1 + y3 * cos3(part of b0)
289 smlsl v26.4s, v9.4h, v7.h[3] //// y1 * cos3 - y3 * sin1(part of b1)
290 smlsl v28.4s, v9.4h, v2.h[1] //// y1 * sin3 - y3 * cos1(part of b2)
291 smlsl v30.4s, v9.4h, v3.h[1] //// y1 * sin1 - y3 * sin3(part of b3)
[all …]

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