| /external/llvm-project/llvm/test/MC/AMDGPU/ |
| D | expressions.s | 122 v_add_u16 v0, (i1+4)/2, v1 label
162 v_add_u16 v0, (i1+100)*2, v0 label
200 v_add_u16 v0, u, v0 label
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| D | vop3-gfx9.s | 785 v_add_u16 v0, s[0:1], v0 label
790 v_add_u16 v0, v[0:1], v0 label
795 v_add_u16 v0, v0, s[0:1] label
800 v_add_u16 v0, v0, v[0:1] label
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| D | literals.s | 561 v_add_u16 v0, vccz, v0 label
700 v_add_u16 v0, src_shared_base, v0 label
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| D | vop3-convert.s | 346 v_add_u16 v1, v2, v3 label
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| D | vop2.s | 444 v_add_u16 v1, v2, v3 clamp label
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| D | vop_dpp.s | 480 v_add_u16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
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| D | gfx10_unsupported.s | 77 v_add_u16 v0, (i1+100)*2, v0 label
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| D | vop_sdwa.s | 472 v_add_u16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
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| D | gfx7_unsupported.s | 823 v_add_u16 v0, (i1+100)*2, v0 label
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | add.v2i16.ll | 127 ; VI-NOT: v_add_u16
130 ; VI-NOT: v_add_u16
147 ; VI-NOT: v_add_u16
150 ; VI-NOT: v_add_u16
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| /external/llvm-project/llvm/docs/ |
| D | AMDGPUOperandSyntax.rst | 1032 v_add_u16 v0, -1, 0 // src0 = 0xFFFF
1038 v_add_u16 v0, 0xff00, v0 // src0 = 0xff00
1039 v_add_u16 v0, 0xffffffffffffff00, v0 // src0 = 0xff00
1040 v_add_u16 v0, -256, v0 // src0 = 0xff00
1057 v_add_u16 v0, 0x1ff00, v0 // truncated bits are not all 0 or 1
1058 v_add_u16 v0, 0xffffffffffff00ff, v0 // truncated bits do not match MSB of the result
1098 v_add_u16 v0, 1.0, 0 // src0 = 0x3C00
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| /external/llvm/test/MC/AMDGPU/ |
| D | vop2.s | 436 v_add_u16 v1, v2, v3 label
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| D | vop_dpp.s | 442 v_add_u16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
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| D | vop_sdwa.s | 449 v_add_u16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
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| /external/llvm/lib/Target/AMDGPU/ |
| D | VIInstructions.td | 60 defm V_ADD_U16 : VOP2Inst <vop2<0,0x26>, "v_add_u16", VOP_I16_I16_I16>;
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | VOP2Instructions.td | 651 defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | VOP2Instructions.td | 626 defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16, add>;
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_lower_to_hw_instr.cpp | 86 return aco_opcode::v_add_u16; in get_reduce_opcode()
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| D | aco_instruction_selection.cpp | 1536 emit_vop2_instruction(ctx, instr, aco_opcode::v_add_u16, dst, true); in visit_alu_instr()
1585 … instr = bld.vop2_e64(aco_opcode::v_add_u16, Definition(dst), src0, as_vgpr(ctx, src1)).instr; in visit_alu_instr()
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| /external/llvm-project/llvm/docs/AMDGPU/ |
| D | AMDGPUAsmGFX8.rst | 882 …v_add_u16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`…
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| D | AMDGPUAsmGFX9.rst | 1069 …v_add_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`…
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