Searched refs:v_ashr_i32_e32 (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | sra.ll | 8 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
9 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
26 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
27 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
28 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
29 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | sra.ll | 8 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
9 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
26 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
27 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
28 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
29 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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| D | ashr.v2i16.ll | 45 ; CI: v_ashr_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
46 ; CI: v_ashr_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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| D | bfe-patterns.ll | 105 ; SI-NEXT: v_ashr_i32_e32 [[BFE:v[0-9]+]], [[SHL]], [[SUB]]
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| /external/llvm-project/llvm/test/MC/AMDGPU/ |
| D | vop2.s | 231 v_ashr_i32_e32 v1, v2, v3 label
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | ashr.ll | 177 ; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0
433 ; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0
580 ; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0
583 ; GFX6-NEXT: v_ashr_i32_e32 v1, s0, v1
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