v_ashrrev_i64 (reference) in projects: external

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Searched refs:v_ashrrev_i64 (Results 1 – 24 of 24) sorted by relevance

/external/llvm-project/llvm/test/MC/AMDGPU/
D	gfx10-constant-bus.s	`19 v_ashrrev_i64 v[0:1], 0x100, s[0:1] label 22 v_ashrrev_i64 v[0:1], s2, s[0:1] label`
D	gfx10_err_pos.s	`647 v_ashrrev_i64 v[0:1], 0x100, s[0:1] label 652 v_ashrrev_i64 v[0:1], s3, s[0:1] label`
D	gfx7_unsupported.s	`880 v_ashrrev_i64 v[0:1], 0x100, s[0:1] label`
/external/llvm/test/CodeGen/AMDGPU/
D	sra.ll	`64 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 90 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 141 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 142 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 143 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 144 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}`
D	sign_extend.ll	`146 ; VI-DAG: v_ashrrev_i64 v{{\[[0-9]+:[0-9]+\]}}, 48, v{{\[[0-9]+:[0-9]+\]}}`
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
D	sra.ll	`94 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 120 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 171 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 172 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 173 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 174 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}`
D	mul_int24.ll	`112 ; VI: v_ashrrev_i64 v{{\[[0-9]+:[0-9]+\]}}, 31, v{{\[[0-9]+:[0-9]+\]}}`
D	llvm.mulo.ll	`322 ; GFX9-NEXT: v_ashrrev_i64 v[5:6], 2, v[4:5]`
D	function-returns.ll	`148 ; GFX89-NEXT: v_ashrrev_i64 v[0:1], 1, v[0:1]`
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
D	ashr.ll	1007 ; GFX8-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1] 1013 ; GFX9-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1] 1063 ; GFX8-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1069 ; GFX9-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1132 ; GFX8-NEXT: v_ashrrev_i64 v[0:1], v0, s[0:1] 1137 ; GFX9-NEXT: v_ashrrev_i64 v[0:1], v0, s[0:1] 1152 ; GFX8-NEXT: v_ashrrev_i64 v[0:1], s0, v[0:1] 1157 ; GFX9-NEXT: v_ashrrev_i64 v[0:1], s0, v[0:1] 1175 ; GFX8-NEXT: v_ashrrev_i64 v[0:1], v4, v[0:1] 1176 ; GFX8-NEXT: v_ashrrev_i64 v[2:3], v6, v[2:3] [all …]
D	ssubsat.ll	5711 ; GFX8-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] 5715 ; GFX8-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] 5772 ; GFX9-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] 5776 ; GFX9-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] 5821 ; GFX10-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7] 5829 ; GFX10-NEXT: v_ashrrev_i64 v[2:3], s1, v[6:7] 5958 ; GFX8-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] 5962 ; GFX8-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] 6022 ; GFX9-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] 6026 ; GFX9-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] [all …]
D	saddsat.ll	5725 ; GFX8-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] 5729 ; GFX8-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] 5786 ; GFX9-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] 5790 ; GFX9-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] 5835 ; GFX10-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7] 5843 ; GFX10-NEXT: v_ashrrev_i64 v[2:3], s1, v[6:7] 5972 ; GFX8-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] 5976 ; GFX8-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] 6036 ; GFX9-NEXT: v_ashrrev_i64 v[8:9], s0, v[6:7] 6040 ; GFX9-NEXT: v_ashrrev_i64 v[0:1], s1, v[6:7] [all …]
/external/mesa3d/src/amd/compiler/
D	aco_validate.cpp	`255 instr->opcode == aco_opcode::v_ashrrev_i64; in validate_ir()`
D	aco_optimizer.cpp	`2453 instr->opcode == aco_opcode::v_ashrrev_i64; in apply_sgprs() 3179 instr->opcode == aco_opcode::v_ashrrev_i64; in select_instruction()`
D	aco_instruction_selection.cpp	`1465 bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst), in visit_alu_instr()`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
D	VOP3Instructions.td	`398 def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, ashr_rev>;`
/external/llvm-project/llvm/lib/Target/AMDGPU/
D	VOP3Instructions.td	`416 def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, ashr_rev>;`
/external/llvm/lib/Target/AMDGPU/
D	SIInstructions.td	`1897 defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64",`
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
D	gfx8_dasm_all.txt	53835 # CHECK: v_ashrrev_i64 v[5:6], v1, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x01,0x05,0x02,0x… 53838 # CHECK: v_ashrrev_i64 v[254:255], v1, v[2:3] ; encoding: [0xfe,0x00,0x91,0xd2,0x01,0x05,0x02,0x… 53841 # CHECK: v_ashrrev_i64 v[5:6], v255, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0xff,0x05,0x02,0x… 53844 # CHECK: v_ashrrev_i64 v[5:6], s1, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x01,0x04,0x02,0x… 53847 # CHECK: v_ashrrev_i64 v[5:6], s101, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x65,0x04,0x02,0x… 53850 # CHECK: v_ashrrev_i64 v[5:6], flat_scratch_lo, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x66,0x04,0… 53853 # CHECK: v_ashrrev_i64 v[5:6], flat_scratch_hi, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x67,0x04,0… 53856 # CHECK: v_ashrrev_i64 v[5:6], vcc_lo, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x6a,0x04,0x02,0x… 53859 # CHECK: v_ashrrev_i64 v[5:6], vcc_hi, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x6b,0x04,0x02,0x… 53862 # CHECK: v_ashrrev_i64 v[5:6], tba_lo, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x6c,0x04,0x02,0x… [all …]
D	gfx9_dasm_all.txt	47904 # CHECK: v_ashrrev_i64 v[5:6], v1, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x01,0x05,0x02,0x… 47907 # CHECK: v_ashrrev_i64 v[254:255], v1, v[2:3] ; encoding: [0xfe,0x00,0x91,0xd2,0x01,0x05,0x02,0x… 47910 # CHECK: v_ashrrev_i64 v[5:6], v255, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0xff,0x05,0x02,0x… 47913 # CHECK: v_ashrrev_i64 v[5:6], s1, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x01,0x04,0x02,0x… 47916 # CHECK: v_ashrrev_i64 v[5:6], s101, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x65,0x04,0x02,0x… 47919 # CHECK: v_ashrrev_i64 v[5:6], flat_scratch_lo, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x66,0x04,0… 47922 # CHECK: v_ashrrev_i64 v[5:6], flat_scratch_hi, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x67,0x04,0… 47925 # CHECK: v_ashrrev_i64 v[5:6], vcc_lo, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x6a,0x04,0x02,0x… 47928 # CHECK: v_ashrrev_i64 v[5:6], vcc_hi, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x6b,0x04,0x02,0x… 47931 # CHECK: v_ashrrev_i64 v[5:6], m0, v[2:3] ; encoding: [0x05,0x00,0x91,0xd2,0x7c,0x04,0x02,0x… [all …]
D	gfx10_dasm_all.txt	22550 # GFX10: v_ashrrev_i64 v[254:255], v1, v[2:3] ; encoding: [0xfe,0x00,0x01,0xd7,0x01,0x05,0x02,0x… 22553 # GFX10: v_ashrrev_i64 v[5:6], -1, v[2:3] ; encoding: [0x05,0x00,0x01,0xd7,0xc1,0x04,0x02,0x… 22556 # GFX10: v_ashrrev_i64 v[5:6], -4.0, v[2:3] ; encoding: [0x05,0x00,0x01,0xd7,0xf7,0x04,0x02,0x… 22559 # GFX10: v_ashrrev_i64 v[5:6], 0, v[2:3] ; encoding: [0x05,0x00,0x01,0xd7,0x80,0x04,0x02,0x… 22562 # GFX10: v_ashrrev_i64 v[5:6], 0.5, v[2:3] ; encoding: [0x05,0x00,0x01,0xd7,0xf0,0x04,0x02,0x… 22565 # GFX10: v_ashrrev_i64 v[5:6], exec_hi, v[2:3] ; encoding: [0x05,0x00,0x01,0xd7,0x7f,0x04,0x02,0x… 22568 # GFX10: v_ashrrev_i64 v[5:6], exec_lo, v[2:3] ; encoding: [0x05,0x00,0x01,0xd7,0x7e,0x04,0x02,0x… 22571 # GFX10: v_ashrrev_i64 v[5:6], m0, v[2:3] ; encoding: [0x05,0x00,0x01,0xd7,0x7c,0x04,0x02,0x… 22574 # GFX10: v_ashrrev_i64 v[5:6], s1, v[2:3] ; encoding: [0x05,0x00,0x01,0xd7,0x01,0x04,0x02,0x… 22577 # GFX10: v_ashrrev_i64 v[5:6], s101, v[2:3] ; encoding: [0x05,0x00,0x01,0xd7,0x65,0x04,0x02,0x… [all …]
/external/llvm-project/llvm/docs/AMDGPU/
D	AMDGPUAsmGFX8.rst	1043 …v_ashrrev_i64 :ref:`vdst<amdgpu_synid8_vdst64_0>`, :ref:`src0<amdgpu_synid…
D	AMDGPUAsmGFX9.rst	1240 …v_ashrrev_i64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src0<amdgp…
D	AMDGPUAsmGFX10.rst	1505 …v_ashrrev_i64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_syni…

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