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Searched refs:v_div_fmas_f32 (Results 1 – 25 of 29) sorted by relevance

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/external/llvm-project/llvm/test/MC/AMDGPU/
Dvop-err.s51 v_div_fmas_f32 v0, s1, s1, s1 label
54 v_div_fmas_f32 v0, v2, v3, -s1 label
57 v_div_fmas_f32 v0, v1, s2, |v3| label
60 v_div_fmas_f32 v0, v1, -v2, -s3 label
63 v_div_fmas_f32 v0, v1, flat_scratch_lo, v3 label
66 v_div_fmas_f32 v0, v1, v2, flat_scratch_hi label
69 v_div_fmas_f32 v0, v1, v2, m0 label
72 v_div_fmas_f32 v0, v1, ttmp2, v2 label
Dgfx10-constant-bus.s28 v_div_fmas_f32 v5, s3, s3, s3 label
31 v_div_fmas_f32 v5, s3, s3, s2 label
34 v_div_fmas_f32 v5, s3, 0x123, v3 label
Dliterals.s810 v_div_fmas_f32 v0, shared_base, v0, v1 label
815 v_div_fmas_f32 v0, v0, shared_limit, v1 label
820 v_div_fmas_f32 v0, v0, v1, private_limit label
824 v_div_fmas_f32 v0, execz, v0, v1 label
828 v_div_fmas_f32 v0, v0, scc, v1 label
832 v_div_fmas_f32 v0, v0, v1, vccz label
Dvop3-literal.s370 v_div_fmas_f32 v5, v1, 0x123, v3 label
374 v_div_fmas_f32 v5, v1, 0x123, 0x123 label
378 v_div_fmas_f32 v5, 0x123, 0x123, 0x123 label
Dgfx10_err_pos.s667 v_div_fmas_f32 v5, s3, 0x123, v3 label
672 v_div_fmas_f32 v5, s3, v3, 0x123 label
677 v_div_fmas_f32 v5, 0x123, v3, s3 label
682 v_div_fmas_f32 v5, s3, s4, v3 label
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.div.fmas.ll7 define float @v_div_fmas_f32(float %a, float %b, float %c, i1 %d) {
8 ; GFX7-LABEL: v_div_fmas_f32:
14 ; GFX7-NEXT: v_div_fmas_f32 v0, v0, v1, v2
17 ; GFX8-LABEL: v_div_fmas_f32:
23 ; GFX8-NEXT: v_div_fmas_f32 v0, v0, v1, v2
26 ; GFX10_W32-LABEL: v_div_fmas_f32:
32 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, v0, v1, v2
35 ; GFX10_W64-LABEL: v_div_fmas_f32:
41 ; GFX10_W64-NEXT: v_div_fmas_f32 v0, v0, v1, v2
98 ; GFX7-NEXT: v_div_fmas_f32 v0, v0, v1, v2
[all …]
Dfrem.ll32 ; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5
208 ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
237 ; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
537 ; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5
556 ; CI-NEXT: v_div_fmas_f32 v3, v3, v5, v6
639 ; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5
658 ; CI-NEXT: v_div_fmas_f32 v3, v3, v5, v6
676 ; CI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
694 ; CI-NEXT: v_div_fmas_f32 v5, v5, v7, v8
798 ; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4
[all …]
Dconstant-bus-restriction.ll183 ; GFX9-NEXT: v_div_fmas_f32 v0, v0, v0, v0
189 ; GFX10-NEXT: v_div_fmas_f32 v0, s2, s2, s2
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.div.fmas.ll20 ; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VB]], [[VA]], [[VC]]
34 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VB]], [[VC]]
48 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], 1.0, [[VC]]
62 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0
81 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
91 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
100 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
115 ; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]]
150 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
Dfrem.ll13 ; GCN: v_div_fmas_f32
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.div.fmas.ll25 ; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], [[VC]]
38 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VB]], [[VC]]
55 ; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], 1.0, [[VC]]
72 ; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0
90 ; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
100 ; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
109 ; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
124 ; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]]
161 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
Dllvm.powi.ll67 ; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
83 ; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
114 ; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
131 ; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
210 ; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
233 ; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
Dfdiv32-to-rcp-folding.ll258 ; GCN-DENORM-DAG: v_div_fmas_f32
259 ; GCN-DENORM-DAG: v_div_fmas_f32
301 ; GCN-DENORM-DAG: v_div_fmas_f32
302 ; GCN-DENORM-DAG: v_div_fmas_f32
328 ; GCN-DENORM: v_div_fmas_f32
397 ; GCN: v_div_fmas_f32
410 ; GCN: v_div_fmas_f32
423 ; GCN: v_div_fmas_f32
437 ; GCN: v_div_fmas_f32
Dfrem.ll39 ; SI-NEXT: v_div_fmas_f32 v2, v2, v4, v5
80 ; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5
335 ; SI-NEXT: v_div_fmas_f32 v2, v2, v4, v5
371 ; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5
405 ; VI-NEXT: v_div_fmas_f32 v3, v3, v6, v7
971 ; SI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
989 ; SI-NEXT: v_div_fmas_f32 v2, v2, v5, v6
1036 ; CI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
1054 ; CI-NEXT: v_div_fmas_f32 v2, v2, v5, v6
1156 ; SI-NEXT: v_div_fmas_f32 v8, v8, v10, v11
[all …]
Dfdiv.ll31 ; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
67 ; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
92 ; GCN: v_div_fmas_f32
303 ; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
339 ; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
Dds-sub-offset.ll46 ; CI-NEXT: v_div_fmas_f32 v1, v1, v1, v1
63 ; GFX9-NEXT: v_div_fmas_f32 v2, v1, v1, v1
232 ; CI-NEXT: v_div_fmas_f32 v1, v1, v1, v1
251 ; GFX9-NEXT: v_div_fmas_f32 v2, v1, v1, v1
Dfdiv.f16.ll21 ; SI: v_div_fmas_f32
Dwave32.ll421 ; GCN: v_div_fmas_f32 v{{[0-9]+}}, {{[vs][0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
450 ; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
486 ; GCN: v_div_fmas_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
/external/mesa3d/src/amd/compiler/
Daco_insert_NOPs.cpp395 … if (instr->opcode == aco_opcode::v_div_fmas_f32 || instr->opcode == aco_opcode::v_div_fmas_f64) in handle_instruction_gfx6()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DVOP3Instructions.td314 // v_div_fmas_f32:
319 def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, []> {
/external/llvm-project/llvm/lib/Target/AMDGPU/
DVOP3Instructions.td325 // v_div_fmas_f32:
330 def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, []> {
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td1843 // v_div_fmas_f32:
1848 defm V_DIV_FMAS_F32 : VOP3_VCC_Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32",
/external/llvm-project/llvm/docs/AMDGPU/
DAMDGPUAsmGFX7.rst1034 …v_div_fmas_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdg…
DAMDGPUAsmGFX8.rst1292 …v_div_fmas_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid…
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dgfx10_dasm_all.txt71262 # GFX10: v_div_fmas_f32 v255, v1, v2, v3 ; encoding: [0xff,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x…
71265 # GFX10: v_div_fmas_f32 v5, -1, v2, v3 ; encoding: [0x05,0x00,0x6f,0xd5,0xc1,0x04,0x0e,0x…
71268 # GFX10: v_div_fmas_f32 v5, -4.0, v2, v3 ; encoding: [0x05,0x00,0x6f,0xd5,0xf7,0x04,0x0e,0x…
71271 # GFX10: v_div_fmas_f32 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x…
71274 # GFX10: v_div_fmas_f32 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x…
71277 # GFX10: v_div_fmas_f32 v5, 0, v2, v3 ; encoding: [0x05,0x00,0x6f,0xd5,0x80,0x04,0x0e,0x…
71280 # GFX10: v_div_fmas_f32 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0x6f,0xd5,0xf0,0x04,0x0e,0x…
71283 # GFX10: v_div_fmas_f32 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x6f,0xd5,0x01,0x83,0x0d,0x…
71286 # GFX10: v_div_fmas_f32 v5, v1, -4.0, v3 ; encoding: [0x05,0x00,0x6f,0xd5,0x01,0xef,0x0d,0x…
71289 # GFX10: v_div_fmas_f32 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x…
[all …]

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