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Searched refs:v_max_f16_e32 (Results 1 – 18 of 18) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dfmax3.ll51 ; VI-DAG: v_max_f16_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]]
52 ; VI-DAG: v_max_f16_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]]
53 ; VI: v_max_f16_e32 [[MAX0:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
54 ; VI: v_max_f16_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]]
55 ; VI: v_max_f16_e32 [[RESULT:v[0-9]+]], [[MAX0]], [[QUIET_C]]
81 ; VI-DAG: v_max_f16_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]]
82 ; VI-DAG: v_max_f16_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]]
83 ; VI: v_max_f16_e32 [[MAX0:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
84 ; VI: v_max_f16_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]]
85 ; VI: v_max_f16_e32 [[RESULT:v[0-9]+]], [[QUIET_C]], [[MAX0]]
[all …]
Dllvm.maxnum.f16.ll58 ; VI-NEXT: v_max_f16_e32 v0, v0, v0
60 ; VI-NEXT: v_max_f16_e32 v1, v1, v1
61 ; VI-NEXT: v_max_f16_e32 v0, v0, v1
83 ; GFX9-NEXT: v_max_f16_e32 v0, v0, v0
85 ; GFX9-NEXT: v_max_f16_e32 v1, v1, v1
86 ; GFX9-NEXT: v_max_f16_e32 v0, v0, v1
136 ; VI-NEXT: v_max_f16_e32 v0, v0, v0
137 ; VI-NEXT: v_max_f16_e32 v0, 0x4200, v0
155 ; GFX9-NEXT: v_max_f16_e32 v0, v0, v0
156 ; GFX9-NEXT: v_max_f16_e32 v0, 0x4200, v0
[all …]
Dfcanonicalize.f16.ll23 ; GFX89: v_max_f16_e32 [[REG:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
51 ; VI: v_max_f16_e32 v0, v0, v0
275 ; VI-DAG: v_max_f16_e32 [[REG1:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
515 ; VI-DAG: v_max_f16_e32 [[CANON_ELT0:v[0-9]+]], v0, v0
516 ; VI-DAG: v_max_f16_e32 v1, v1, v1
532 ; VI-DAG: v_max_f16_e32 [[CANON_ELT2:v[0-9]+]], v1, v1
534 ; VI-DAG: v_max_f16_e32 [[CANON_ELT0:v[0-9]+]], v0, v0
554 ; GFX9-NEXT: v_max_f16_e32 v0, v0, v0
561 ; VI-NEXT: v_max_f16_e32 v0, v0, v0
637 ; GFX9-DAG: v_max_f16_e32 v0, v0, v0
[all …]
Dreduction.ll446 ; VI-DAG: v_max_f16_e32 [[CANON0:v[0-9]+]], v0, v0
447 ; VI-DAG: v_max_f16_e32 [[CANON2:v[0-9]+]], v1, v1
449 ; VI-DAG: v_max_f16_e32 [[MAX0:v[0-9]+]], [[CANON1]], [[CANON3]]
450 ; VI-DAG: v_max_f16_e32 [[MAX1:v[0-9]+]], [[CANON0]], [[CANON2]]
451 ; VI: v_max_f16_e32 v0, [[MAX1]], [[MAX0]]
471 ; VI-DAG: v_max_f16_e32 [[CANON0:v[0-9]+]], v0, v0
472 ; VI-DAG: v_max_f16_e32 [[CANON2:v[0-9]+]], v1, v1
496 ; XVI-NEXT: v_max_f16_e32 v0, v0, v1
497 ; XVI-NEXT: v_max_f16_e32 v0, v0, v2
508 ; VI-DAG: v_max_f16_e32 [[CANON0:v[0-9]+]], v0, v0
[all …]
Dfmax_legacy.f16.ll22 ; GFX9-NNAN-NEXT: v_max_f16_e32 v0, v0, v1
35 ; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v1
99 ; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v1
179 ; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v2
180 ; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v3
283 ; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v3
285 ; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v2
433 ; VI-NNAN-NEXT: v_max_f16_e32 v3, v3, v7
435 ; VI-NNAN-NEXT: v_max_f16_e32 v2, v2, v6
437 ; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v5
[all …]
Dllvm.minnum.f16.ll58 ; VI-NEXT: v_max_f16_e32 v0, v0, v0
60 ; VI-NEXT: v_max_f16_e32 v1, v1, v1
83 ; GFX9-NEXT: v_max_f16_e32 v0, v0, v0
85 ; GFX9-NEXT: v_max_f16_e32 v1, v1, v1
159 ; VI-NEXT: v_max_f16_e32 v0, v0, v0
178 ; GFX9-NEXT: v_max_f16_e32 v0, v0, v0
227 ; VI-NEXT: v_max_f16_e32 v0, v0, v0
246 ; GFX9-NEXT: v_max_f16_e32 v0, v0, v0
Dfcanonicalize.ll472 ; GFX9: v_max_f16_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
527 ; GFX8: v_max_f16_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
528 ; GFX9: v_max_f16_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
544 ; GFX8: v_max_f16_e32
Dfmed3.ll890 ; VI: v_max_f16_e32 v{{[0-9]+}}, 2.0
Dfneg-combines.ll639 ; VI: v_max_f16_e32 [[QUIET:v[0-9]+]], [[A]], [[A]]
664 ; VI: v_max_f16_e32 [[RESULT:v[0-9]+]], 0.15915494, [[NEG_QUIET]]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dliteral_gfx9.txt39 # GFX9: v_max_f16_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x5a]
120 # GFX9: v_max_f16_e32 v0, src_execz, v0 ; encoding: [0xfc,0x00,0x00,0x5a]
Dvop2_vi.txt252 # VI: v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
Dgfx8_dasm_all.txt41715 # CHECK: v_max_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x5a]
41718 # CHECK: v_max_f16_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x5b]
41721 # CHECK: v_max_f16_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x5a]
41724 # CHECK: v_max_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x5a]
41727 # CHECK: v_max_f16_e32 v5, s101, v2 ; encoding: [0x65,0x04,0x0a,0x5a]
41730 # CHECK: v_max_f16_e32 v5, flat_scratch_lo, v2 ; encoding: [0x66,0x04,0x0a,0x5a]
41733 # CHECK: v_max_f16_e32 v5, flat_scratch_hi, v2 ; encoding: [0x67,0x04,0x0a,0x5a]
41736 # CHECK: v_max_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x5a]
41739 # CHECK: v_max_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x5a]
41742 # CHECK: v_max_f16_e32 v5, tba_lo, v2 ; encoding: [0x6c,0x04,0x0a,0x5a]
[all …]
Dgfx9_dasm_all.txt34818 # CHECK: v_max_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x5a]
34821 # CHECK: v_max_f16_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x5b]
34824 # CHECK: v_max_f16_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x5a]
34827 # CHECK: v_max_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x5a]
34830 # CHECK: v_max_f16_e32 v5, s101, v2 ; encoding: [0x65,0x04,0x0a,0x5a]
34833 # CHECK: v_max_f16_e32 v5, flat_scratch_lo, v2 ; encoding: [0x66,0x04,0x0a,0x5a]
34836 # CHECK: v_max_f16_e32 v5, flat_scratch_hi, v2 ; encoding: [0x67,0x04,0x0a,0x5a]
34839 # CHECK: v_max_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x5a]
34842 # CHECK: v_max_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x5a]
34845 # CHECK: v_max_f16_e32 v5, m0, v2 ; encoding: [0x7c,0x04,0x0a,0x5a]
[all …]
Dgfx10_dasm_all.txt80835 # GFX10: v_max_f16_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x73]
80838 # GFX10: v_max_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x72]
80841 # GFX10: v_max_f16_e32 v5, -4.0, v2 ; encoding: [0xf7,0x04,0x0a,0x72]
80844 # GFX10: v_max_f16_e32 v5, 0, v2 ; encoding: [0x80,0x04,0x0a,0x72]
80847 # GFX10: v_max_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x72]
80850 # GFX10: v_max_f16_e32 v5, 0x3456, v2 ; encoding: [0xff,0x04,0x0a,0x72,0x56,0x34,0x00,0x…
80853 # GFX10: v_max_f16_e32 v5, 0xfe0b, v2 ; encoding: [0xff,0x04,0x0a,0x72,0x0b,0xfe,0x00,0x…
80856 # GFX10: v_max_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x72]
80859 # GFX10: v_max_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x72]
80862 # GFX10: v_max_f16_e32 v5, m0, v2 ; encoding: [0x7c,0x04,0x0a,0x72]
[all …]
/external/llvm-project/llvm/test/MC/AMDGPU/
Dvop2.s480 v_max_f16_e32 v1, v2, v3 label
Dgfx7_unsupported.s1954 v_max_f16_e32 v255, v1, v2 label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvop2_vi.txt237 # VI: v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
/external/llvm-project/llvm/docs/
DAMDGPUUsage.rst8888 v_max_f16_e32 v1, v2, v3