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Searched refs:v_mul_f32 (Results 1 – 25 of 33) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dfmul.ll6 ; GCN: v_mul_f32
17 ; GCN: v_mul_f32
18 ; GCN: v_mul_f32
30 ; GCN: v_mul_f32
31 ; GCN: v_mul_f32
32 ; GCN: v_mul_f32
33 ; GCN: v_mul_f32
49 ; GCN: v_mul_f32
50 ; GCN-NOT: v_mul_f32
60 ; GCN: v_mul_f32
[all …]
Dllvm.sin.ll14 ; GCN: v_mul_f32
26 ; GCN: v_mul_f32
27 ; GCN: v_mul_f32
42 ; GCN: v_mul_f32
57 ; GCN: v_mul_f32
71 ; GCN: v_mul_f32
86 ; GCN: v_mul_f32
101 ; GCN: v_mul_f32
114 ; GCN: v_mul_f32
115 ; GCN: v_mul_f32
[all …]
Damdgcn-ieee.ll9 ; GCN-NOT: v_mul_f32
24 ; GCN-NOT: v_mul_f32
39 ; GCN-NOT: v_mul_f32
54 ; GCN-NOT: v_mul_f32
69 ; GCN-NOT: v_mul_f32
84 ; GCN-NOT: v_mul_f32
99 ; GCN-NOT: v_mul_f32
114 ; GCN-NOT: v_mul_f32
129 ; GCN-NOT: v_mul_f32
144 ; GCN-NOT: v_mul_f32
[all …]
Dearly-if-convert.ll79 ; GCN: v_mul_f32
80 ; GCN: v_mul_f32
81 ; GCN: v_mul_f32
82 ; GCN: v_mul_f32
83 ; GCN: v_mul_f32
84 ; GCN: v_mul_f32
85 ; GCN: v_mul_f32
86 ; GCN: v_mul_f32
87 ; GCN: v_mul_f32
117 ; GCN: v_mul_f32
[all …]
Dfdiv.ll78 ; GCN: v_mul_f32
80 ; GCN: v_mul_f32
81 ; GCN: v_mul_f32
Dfdiv.f16.ll17 ; SI: v_mul_f32
Dmad-mix.ll402 ; GFX9: v_mul_f32
416 ; GFX9: v_mul_f32
Dfpext-free.ll40 ; GCN: v_mul_f32
/external/llvm/test/CodeGen/AMDGPU/
Dfmul.ll6 ; GCN: v_mul_f32
21 ; GCN: v_mul_f32
22 ; GCN: v_mul_f32
34 ; GCN: v_mul_f32
35 ; GCN: v_mul_f32
36 ; GCN: v_mul_f32
37 ; GCN: v_mul_f32
53 ; GCN: v_mul_f32
54 ; GCN-NOT: v_mul_f32
64 ; GCN: v_mul_f32
[all …]
Dfdiv.ll22 ; SI-DAG: v_mul_f32
27 ; I754-DAG: v_mul_f32
45 ; SI-DAG: v_mul_f32
61 ; SI-DAG: v_mul_f32
81 ; SI-DAG: v_mul_f32
83 ; SI-DAG: v_mul_f32
110 ; SI-DAG: v_mul_f32
112 ; SI-DAG: v_mul_f32
132 ; SI-DAG: v_mul_f32
134 ; SI-DAG: v_mul_f32
[all …]
Dllvm.sin.ll11 ; SI: v_mul_f32
22 ; SI: v_mul_f32
23 ; SI: v_mul_f32
37 ; SI: v_mul_f32
50 ; SI: v_mul_f32
64 ; SI: v_mul_f32
77 ; SI: v_mul_f32
90 ; SI: v_mul_f32
/external/mesa3d/src/amd/compiler/tests/
Dtest_optimizer.cpp37 writeout(0, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], neg_b));
44 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x123456u), neg_a));
49 writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), neg_neg_a, inputs[1]));
55 writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), abs_neg_a, inputs[1]));
61 writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), neg_abs_a, inputs[1]));
65 … writeout(5, bld.vop2_dpp(aco_opcode::v_mul_f32, bld.def(v1), neg_a, inputs[1], dpp_row_sl(1)));
78 writeout(8, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], neg_c));
/external/mesa3d/src/gallium/drivers/radeonsi/glsl_tests/
Ddiv.glsl8 ; GCN-NEXT: v_mul_f32
/external/llvm-project/llvm/test/MC/AMDGPU/
Dreg-syntax-extra.s153 v_mul_f32 v0, null, v2 label
Dexpressions.s265 v_mul_f32 v0, foo+2, v2 label
Dvop2.s171 v_mul_f32 v1, v2, v3 label
Dvop3.s253 v_mul_f32 v1, v3, s5 label
Dvop_dpp.s404 v_mul_f32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
Dvop_sdwa.s400 v_mul_f32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
/external/llvm/test/MC/AMDGPU/
Dvop3.s235 v_mul_f32 v1, v3, s5 label
Dvop2.s146 v_mul_f32 v1, v2, v3 label
Dvop_dpp.s366 v_mul_f32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
Dvop_sdwa.s373 v_mul_f32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
/external/mesa3d/src/amd/compiler/
Daco_instruction_selection.cpp755 bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp); in emit_vop2_instruction()
809 bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp); in emit_vop3a_instruction()
1030 Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val); in emit_scaled_op()
1032 scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled); in emit_scaled_op()
1780 emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true); in visit_alu_instr()
1860 bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, ma)); in visit_alu_instr()
1863 bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, ma)); in visit_alu_instr()
1901 … src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src)); in visit_alu_instr()
1923 … src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src)); in visit_alu_instr()
2118 Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, src); in visit_alu_instr()
[all …]
Daco_optimizer.cpp546 case aco_opcode::v_mul_f32: in can_swap_operands()
1275 case aco_opcode::v_mul_f32: { /* omod */ in label_instruction()
2833 else if (instr->opcode == aco_opcode::v_mul_f32 && !instr->isVOP3()) { in combine_instruction()

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