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Searched refs:val16 (Results 1 – 25 of 57) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Dhalf.ll53 %val16 = load half, half* %addr
54 %val32 = fpext half %val16 to float
62 %val16 = load half, half* %addr
63 %val32 = fpext half %val16 to double
71 %val16 = fptrunc float %in to half
72 store half %val16, half* %addr
80 %val16 = fptrunc double %in to half
81 store half %val16, half* %addr
Daddsub_ext.ll148 %val16 = add i16 %val16_tmp, 123
152 %rhs32_zext = zext i16 %val16 to i32
164 %rhs64_zext = zext i16 %val16 to i64
175 %rhs32_sext = sext i16 %val16 to i32
186 %rhs64_sext = sext i16 %val16 to i64
203 %cmp_sext = sext i16 %val16 to i64
223 %val16 = add i16 %val16_tmp, 123
227 %rhs32_zext = zext i16 %val16 to i32
239 %rhs64_zext = zext i16 %val16 to i64
250 %rhs32_sext = sext i16 %val16 to i32
[all …]
Dfloatdp_1source.ll109 %val16 = load volatile half, half* @varhalf
113 %val16to32 = fpext half %val16 to float
117 %val16to64 = fpext half %val16 to double
/external/llvm/test/CodeGen/ARM/
Dhalf.ll36 %val16 = load half, half* %addr
37 %val32 = fpext half %val16 to float
49 %val16 = load half, half* %addr
50 %val32 = fpext half %val16 to double
60 %val16 = fptrunc float %in to half
61 store half %val16, half* %addr
71 %val16 = fptrunc double %in to half
72 store half %val16, half* %addr
Dldaex-stlex.ll50 %val16 = trunc i32 %val to i16
51 ret i16 %val16
/external/llvm/test/CodeGen/NVPTX/
Dhalf.ll36 %val16 = load half, half addrspace(1)* %in
37 %val32 = fpext half %val16 to float
46 %val16 = load half, half addrspace(1)* %in
47 %val64 = fpext half %val16 to double
57 %val16 = fptrunc float %val32 to half
58 store half %val16, half addrspace(1)* %out
67 %val16 = fptrunc double %val32 to half
68 store half %val16, half addrspace(1)* %out
/external/llvm-project/llvm/test/CodeGen/NVPTX/
Dhalf.ll40 %val16 = load half, half addrspace(1)* %in
41 %val32 = fpext half %val16 to float
50 %val16 = load half, half addrspace(1)* %in
51 %val64 = fpext half %val16 to double
61 %val16 = fptrunc float %val32 to half
62 store half %val16, half addrspace(1)* %out
71 %val16 = fptrunc double %val32 to half
72 store half %val16, half addrspace(1)* %out
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dextend-bit-ops-i16.ll12 %val16 = and i16 %c, %a
13 %val32 = zext i16 %val16 to i32
27 %val16 = or i16 %c, %a
28 %val32 = zext i16 %val16 to i32
42 %val16 = xor i16 %c, %a
43 %val32 = zext i16 %val16 to i32
/external/llvm-project/llvm/test/CodeGen/ARM/
Dhalf.ll43 %val16 = load half, half* %addr
44 %val32 = fpext half %val16 to float
58 %val16 = load half, half* %addr
59 %val32 = fpext half %val16 to double
70 %val16 = fptrunc float %in to half
71 store half %val16, half* %addr
82 %val16 = fptrunc double %in to half
83 store half %val16, half* %addr
Dldaex-stlex.ll50 %val16 = trunc i32 %val to i16
51 ret i16 %val16
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dhalf.ll61 %val16 = load half, half* %addr
62 %val32 = fpext half %val16 to float
72 %val16 = load half, half* %addr
73 %val32 = fpext half %val16 to double
83 %val16 = fptrunc float %in to half
84 store half %val16, half* %addr
94 %val16 = fptrunc double %in to half
95 store half %val16, half* %addr
Dmisched-fusion-addr.ll22 %val16 = trunc i64 %add to i16
23 store volatile i16 %val16, i16* @var_16bit
34 %val16 = load volatile i16, i16* @var_16bit
35 %ext = zext i16 %val16 to i64
Daddsub_ext.ll161 %val16 = add i16 %val16_tmp, 123
165 %rhs32_zext = zext i16 %val16 to i32
178 %rhs64_zext = zext i16 %val16 to i64
191 %rhs32_sext = sext i16 %val16 to i32
202 %rhs64_sext = sext i16 %val16 to i64
219 %cmp_sext = sext i16 %val16 to i64
240 %val16 = add i16 %val16_tmp, 123
244 %rhs32_zext = zext i16 %val16 to i32
257 %rhs64_zext = zext i16 %val16 to i64
270 %rhs32_sext = sext i16 %val16 to i32
[all …]
Dfloatdp_1source.ll109 %val16 = load volatile half, half* @varhalf
113 %val16to32 = fpext half %val16 to float
117 %val16to64 = fpext half %val16 to double
Darm64_32-atomics.ll93 %val16 = trunc i64 %val to i16
94 ret i16 %val16
133 %val16 = trunc i64 %val to i16
134 ret i16 %val16
/external/webrtc/rtc_base/
Dbit_buffer_unittest.cc49 uint16_t val16; in TEST() local
56 EXPECT_TRUE(buffer.ReadUInt16(&val16)); in TEST()
57 EXPECT_EQ(0xDEF1u, val16); in TEST()
66 uint16_t val16; in TEST() local
75 EXPECT_TRUE(buffer.ReadUInt16(&val16)); in TEST()
76 EXPECT_EQ(0xEF12u, val16); in TEST()
101 uint16_t val16; in TEST() local
107 EXPECT_TRUE(buffer.ReadUInt16(&val16)); in TEST()
108 EXPECT_EQ(0xDCBAu, val16); in TEST()
391 uint16_t val16; in TEST() local
[all …]
/external/deqp/framework/delibs/debase/
DdeFloat16.c489 float deFloat16To32 (deFloat16 val16) in deFloat16To32() argument
502 sign = ((deUint32)val16 >> 15u) & 0x00000001u; in deFloat16To32()
503 expotent = ((deUint32)val16 >> 10u) & 0x0000001fu; in deFloat16To32()
504 mantissa = (deUint32)val16 & 0x000003ffu; in deFloat16To32()
551 double deFloat16To64 (deFloat16 val16) in deFloat16To64() argument
564 sign = ((deUint32)val16 >> 15u) & 0x00000001u; in deFloat16To64()
565 expotent = ((deUint32)val16 >> 10u) & 0x0000001fu; in deFloat16To64()
566 mantissa = (deUint32)val16 & 0x000003ffu; in deFloat16To64()
DdeFloat16.h54 float deFloat16To32 (deFloat16 val16);
61 double deFloat16To64 (deFloat16 val16);
/external/llvm/test/CodeGen/X86/
Dhalf.ll42 %val16 = load half, half* %addr
43 %val32 = fpext half %val16 to float
54 %val16 = load half, half* %addr
55 %val32 = fpext half %val16 to double
64 %val16 = fptrunc float %in to half
65 store half %val16, half* %addr
74 %val16 = fptrunc double %in to half
75 store half %val16, half* %addr
/external/llvm-project/llvm/test/CodeGen/RISCV/
Dselect-cc.ll89 %val16 = select i1 %tst8, i32 %val14, i32 %val15
92 %tst9 = icmp slt i32 %val16, %val17
93 %val18 = select i1 %tst9, i32 %val16, i32 %val17
/external/llvm-project/llvm/test/CodeGen/Mips/
Dnacl-reserved-regs.ll23 %val16 = load volatile i32, i32* @var
39 store volatile i32 %val16, i32* @var
/external/llvm-project/llvm/test/MC/AArch64/
Delf-globaladdress.ll18 %val16 = load i16, i16* @var16
19 store volatile i16 %val16, i16* @var16
/external/llvm/test/MC/AArch64/
Delf-globaladdress.ll18 %val16 = load i16, i16* @var16
19 store volatile i16 %val16, i16* @var16
/external/llvm/test/CodeGen/Mips/
Dnacl-reserved-regs.ll23 %val16 = load volatile i32, i32* @var
39 store volatile i32 %val16, i32* @var
/external/llvm-project/polly/test/ScopDetect/
Dprofitability-large-basic-blocks.ll48 %val16 = fadd float %val15, 1.0
49 %val17 = fadd float %val16, 1.0

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