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/external/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
Dscalar-cmp-cmp-log-sel.ll8 i8 %val5, i8 %val6) {
12 %sel = select i1 %and, i8 %val5, i8 %val6
19 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i8 %val5, i8 %val6
23 i16 %val5, i16 %val6) {
27 %sel = select i1 %and, i16 %val5, i16 %val6
34 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i16 %val5, i16 %val6
38 i32 %val5, i32 %val6) {
42 %sel = select i1 %and, i32 %val5, i32 %val6
49 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i32 %val5, i32 %val6
53 i64 %val5, i64 %val6) {
[all …]
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dvec-cmp-cmp-logic-select.ll8 …0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {
19 %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
23 …<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
35 %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
39 …i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i8> %val5, <16 x i8> %val6) {
52 %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
56 …> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i16> %val5, <16 x i16> %val6) {
75 %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
79 …x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x i8> %val4, <32 x i8> %val5, <32 x i8> %val6) {
98 %sel = select <32 x i1> %and, <32 x i8> %val5, <32 x i8> %val6
[all …]
Dspill-01.ll53 %val6 = load i32, i32 *%ptr6
63 store i32 %val6, i32 *%ptr6
91 %val6 = load i32, i32 *%ptr6
103 store i32 %val6, i32 *%ptr6
133 %val6 = load i64, i64 *%ptr6
145 store i64 %val6, i64 *%ptr6
179 %val6 = load float, float *%ptr6
192 store float %val6, float *%ptr6
223 %val6 = load double, double *%ptr6
236 store double %val6, double *%ptr6
[all …]
Dcond-move-10.ll32 %val6 = load i64, i64 *%ptr6
45 %add6 = add i64 %add5, %val6
78 %val6 = load i32, i32 *%ptr6
91 %add6 = add i32 %add5, %val6
Dint-add-12.ll142 %val6 = load volatile i64, i64 *%ptr
163 %add6 = add i64 %val6, 127
182 %new6 = phi i64 [ %val6, %entry ], [ %add6, %add ]
225 %val6 = load volatile i64, i64 *%ptr
246 %add6 = add i64 %val6, -128
265 %new6 = phi i64 [ %val6, %entry ], [ %add6, %add ]
Dint-add-11.ll143 %val6 = load volatile i32, i32 *%ptr
164 %add6 = add i32 %val6, 127
183 %new6 = phi i32 [ %val6, %entry ], [ %add6, %add ]
226 %val6 = load volatile i32, i32 *%ptr
247 %add6 = add i32 %val6, -128
266 %new6 = phi i32 [ %val6, %entry ], [ %add6, %add ]
/external/llvm/test/CodeGen/SystemZ/
Dspill-01.ll53 %val6 = load i32 , i32 *%ptr6
63 store i32 %val6, i32 *%ptr6
91 %val6 = load i32 , i32 *%ptr6
103 store i32 %val6, i32 *%ptr6
133 %val6 = load i64 , i64 *%ptr6
145 store i64 %val6, i64 *%ptr6
179 %val6 = load float , float *%ptr6
192 store float %val6, float *%ptr6
223 %val6 = load double , double *%ptr6
236 store double %val6, double *%ptr6
[all …]
Dint-add-12.ll142 %val6 = load volatile i64 , i64 *%ptr
163 %add6 = add i64 %val6, 127
182 %new6 = phi i64 [ %val6, %entry ], [ %add6, %add ]
225 %val6 = load volatile i64 , i64 *%ptr
246 %add6 = add i64 %val6, -128
265 %new6 = phi i64 [ %val6, %entry ], [ %add6, %add ]
Dint-add-11.ll143 %val6 = load volatile i32 , i32 *%ptr
164 %add6 = add i32 %val6, 127
183 %new6 = phi i32 [ %val6, %entry ], [ %add6, %add ]
226 %val6 = load volatile i32 , i32 *%ptr
247 %add6 = add i32 %val6, -128
266 %new6 = phi i32 [ %val6, %entry ], [ %add6, %add ]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dfloatdp_2source.ll25 %val6 = fmul float %val1, %val2
26 %val7 = fsub float -0.0, %val6
53 %val6 = fmul double %val1, %val2
54 %val7 = fsub double -0.0, %val6
Daddsub-shifted.ll51 %val6 = add i64 %shift6, %lhs64
52 store volatile i64 %val6, i64* @var64
113 %val6 = add i64 %shift6, %lhs64
114 store volatile i64 %val6, i64* @var64
172 %val6 = add i64 %shift6, %lhs64
173 store volatile i64 %val6, i64* @var64
292 %val6 = sub i64 0, %shift6
293 %tst6 = icmp ne i64 %lhs64, %val6
Dregress-w29-reserved-with-fp.ll15 %val6 = load volatile i32, i32* @var
30 store volatile i32 %val6, i32* @var
/external/llvm/test/CodeGen/AArch64/
Dfloatdp_2source.ll25 %val6 = fmul float %val1, %val2
26 %val7 = fsub float -0.0, %val6
53 %val6 = fmul double %val1, %val2
54 %val7 = fsub double -0.0, %val6
Daddsub-shifted.ll48 %val6 = add i64 %shift6, %lhs64
49 store volatile i64 %val6, i64* @var64
110 %val6 = add i64 %shift6, %lhs64
111 store volatile i64 %val6, i64* @var64
169 %val6 = add i64 %shift6, %lhs64
170 store volatile i64 %val6, i64* @var64
289 %val6 = sub i64 0, %shift6
290 %tst6 = icmp ne i64 %lhs64, %val6
Dregress-w29-reserved-with-fp.ll15 %val6 = load volatile i32, i32* @var
30 store volatile i32 %val6, i32* @var
/external/ruy/ruy/
Dpack_arm.cc2299 int8x8_t val0, val1, val2, val3, val4, val5, val6, val7, val8, val9, val10, in Pack8bitRowMajorForNeon() local
2319 val6 = load_and_convert(src_ptr + 6 * src_stride); in Pack8bitRowMajorForNeon()
2338 val6 = val0; in Pack8bitRowMajorForNeon()
2361 val6 = load_and_convert(src_ptr + 6 * src_stride); in Pack8bitRowMajorForNeon()
2386 sums16_1 = vaddq_s16(sums16_1, vaddl_s8(val6, val7)); in Pack8bitRowMajorForNeon()
2407 transpose_8bit_vals(val6, val7); in Pack8bitRowMajorForNeon()
2414 transpose_16bit_vals(val4, val6); in Pack8bitRowMajorForNeon()
2422 transpose_32bit_vals(val2, val6); in Pack8bitRowMajorForNeon()
2440 vst1q_s8(dst_ptr, vcombine_s8(val6, val14)); in Pack8bitRowMajorForNeon()
/external/llvm-project/llvm/test/CodeGen/ARM/
Dgpr-paired-spill-thumbinst.ll14 %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
27 store volatile i64 %val6, i64* %addr
Dinlineasm-64bit.ll13 define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6…
37 …"r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
39 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
40 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
/external/llvm-project/llvm/test/CodeGen/RISCV/
Dselect-cc.ll69 %val6 = select i1 %tst3, i32 %val4, i32 %val5
72 %tst4 = icmp uge i32 %val6, %val7
73 %val8 = select i1 %tst4, i32 %val6, i32 %val7
/external/llvm/test/CodeGen/ARM/
Dinlineasm-64bit.ll13 define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6…
37 …"r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
39 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
40 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
/external/llvm/test/CodeGen/AMDGPU/
Dds_read2_offset_order.ll41 %val6 = load float, float addrspace(3)* %ptr6
42 %add6 = fadd float %add5, %val6
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dds_read2_offset_order.ll39 %val6 = load float, float addrspace(3)* %ptr6
40 %add6 = fadd float %add5, %val6
/external/llvm-project/llvm/test/CodeGen/Mips/
Dnacl-reserved-regs.ll13 %val6 = load volatile i32, i32* @var
29 store volatile i32 %val6, i32* @var
/external/llvm/test/CodeGen/Mips/
Dnacl-reserved-regs.ll13 %val6 = load volatile i32, i32* @var
29 store volatile i32 %val6, i32* @var
/external/tensorflow/tensorflow/compiler/tests/
Ddynamic_stitch_test.py85 val6 = np.array([[20, 21], [30, 31], [50, 51]], dtype=np.float32)
91 [val1, val2, val3], [val4, val5, val6], expected=expected)

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