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Searched refs:vcc (Results 1 – 25 of 807) sorted by relevance

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/external/llvm-project/llvm/test/MC/AMDGPU/
Dvopc-vi.s5 v_cmp_class_f16 vcc, v2, v4
9 v_cmpx_class_f16 vcc, v2, v4
13 v_cmp_f_f16 vcc, v2, v4
17 v_cmp_lt_f16 vcc, v2, v4
21 v_cmp_eq_f16 vcc, v2, v4
25 v_cmp_le_f16 vcc, v2, v4
29 v_cmp_gt_f16 vcc, v2, v4
33 v_cmp_lg_f16 vcc, v2, v4
37 v_cmp_ge_f16 vcc, v2, v4
41 v_cmp_o_f16 vcc, v2, v4
[all …]
Dgfx10_unsupported.s71 v_add_i32_e32 v0, vcc, 0.5, v0
101 v_add_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
104 v_addc_co_u32 v0, vcc, shared_base, v0, vcc
107 v_addc_co_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
110 v_addc_co_u32_e32 v3, vcc, 12345, v3, vcc
116 v_addc_co_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_se…
119 v_addc_u32 v0, vcc, exec_hi, v0, vcc
122 v_addc_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
131 v_addc_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:B…
143 v_cmp_f_i16 vcc, -1, v2
[all …]
Dgfx9_unsupported.s154 v_add_co_ci_u32_dpp v0, vcc, v0, v0, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1
157 v_add_co_ci_u32_e32 v255, vcc, v1, v2, vcc
187 v_addc_u32 v0, vcc, exec_hi, v0, vcc
190 v_addc_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
199 v_addc_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:B…
211 v_cmps_eq_f32 vcc, -1, v2
217 v_cmps_eq_f64 vcc, -1, v[2:3]
223 v_cmps_f_f32 vcc, -1, v2
229 v_cmps_f_f64 vcc, -1, v[2:3]
235 v_cmps_ge_f32 vcc, -1, v2
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dvccz-corrupt-bug-workaround.mir6 # CHECK: $vcc = V_CMP_EQ_F32
8 # SI-NEXT: $vcc = S_MOV_B64 $vcc
9 # CHECK-NEXT: S_CBRANCH_VCCZ %bb.2, implicit killed $vcc
20 $vcc = V_CMP_EQ_F32_e64 0, 0, 0, undef $sgpr2, 0, implicit $mode, implicit $exec
21 S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
62 S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
89 # Test that after reloading vcc spilled to a vgpr, we insert any necessary
93 # CHECK: $vcc_lo = V_READLANE_B32 $vgpr0, 8, implicit-def $vcc
95 # SI: $vcc = S_MOV_B64 $vcc
96 # GFX9: $vcc = S_MOV_B64 $vcc
[all …]
Doptimize-negated-cond-exec-masking.mir5 # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
6 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
13 V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
14 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
15 S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
27 # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
28 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
36 $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
37 S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
50 # GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
[all …]
Dssubsat.ll12 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
43 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
51 ; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v1
58 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
59 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
75 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v1
82 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
83 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
89 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v1
96 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
[all …]
Dllvm.mulo.ll17 ; SI-NEXT: v_add_i32_e32 v1, vcc, v8, v7
18 ; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v6, vcc
19 ; SI-NEXT: v_add_i32_e32 v6, vcc, v1, v5
21 ; SI-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
22 ; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v9, vcc
23 ; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v3
24 ; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
25 ; SI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
26 ; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
37 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v6, v5
[all …]
Dbypass-div.ll14 ; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[3:4]
16 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
21 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v2, v3
22 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v3, vcc
27 ; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, 0, v4
28 ; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, 0, v5, vcc
47 ; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v14, v12
49 ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v11, vcc
51 ; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v12, v14
54 ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v11, v13, vcc
[all …]
Dudiv64.ll31 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
32 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
38 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
39 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
42 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
43 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
44 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc
45 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
47 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
48 ; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
[all …]
Durem64.ll33 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
34 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
40 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
41 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
44 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
45 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
46 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc
47 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
49 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
50 ; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
[all …]
Dsrem64.ll33 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
34 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
40 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
41 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
44 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
45 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
46 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc
47 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
49 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
50 ; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
[all …]
Dreduce-saveexec.mir5 # GCN: $exec = S_AND_B64 $exec, killed $vcc
11 $vcc = IMPLICIT_DEF
12 $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc
18 # GCN: $exec = S_AND_B64 killed $vcc, $exec
24 $vcc = IMPLICIT_DEF
25 $sgpr0_sgpr1 = S_AND_B64 killed $vcc, $exec, implicit-def $scc
31 # GCN: $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc
37 $vcc = IMPLICIT_DEF
38 $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc
44 # GCN: $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 $vcc
[all …]
Dsdiv64.ll38 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
39 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
45 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
46 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc
49 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4
50 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc
51 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc
52 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
54 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
55 ; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
[all …]
Dinsert-skip-from-vcc.mir19 $vcc = S_AND_B64 $exec, killed $sgpr0_sgpr1, implicit-def dead $scc
20 S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
36 $vcc = S_AND_B64 $exec, -1, implicit-def dead $scc
37 S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
53 $vcc = S_AND_B64 $exec, -1, implicit-def dead $scc
54 S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
59 # GCN: $vcc = S_AND_B64 $exec, -1, implicit-def $scc
70 $vcc = S_AND_B64 $exec, -1, implicit-def $scc
71 S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
77 # GCN: $vcc = S_AND_B64 $exec, -1, implicit-def $scc
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dsrem.i64.ll13 ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
15 ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
20 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v2, v4
21 ; CHECK-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
29 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v0, v7
30 ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc
31 ; CHECK-NEXT: v_sub_i32_e32 v9, vcc, 0, v5
38 ; CHECK-NEXT: v_subb_u32_e32 v10, vcc, 0, v3, vcc
45 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v11, v12
46 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v11, v14
[all …]
Dsdiv.i64.ll13 ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
15 ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
20 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v2, v4
21 ; CHECK-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
29 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v0, v8
30 ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v8, vcc
31 ; CHECK-NEXT: v_sub_i32_e32 v10, vcc, 0, v5
38 ; CHECK-NEXT: v_subb_u32_e32 v11, vcc, 0, v3, vcc
45 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, v12, v13
46 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, v12, v15
[all …]
Durem.i64.ll13 ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
15 ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
21 ; CHECK-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
22 ; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc
35 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v10, v8
39 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v11
44 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v11
45 ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
46 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v13, v9
47 ; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
[all …]
Dudiv.i64.ll13 ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
15 ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
21 ; CHECK-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
22 ; CHECK-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc
35 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v10, v8
39 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v11
44 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v11
45 ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
46 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v13, v9
47 ; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
[all …]
Dsrem.i32.ll13 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
14 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v3
18 ; GISEL-NEXT: v_sub_i32_e32 v4, vcc, 0, v1
24 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v4
27 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
28 ; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v0, v1
29 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
30 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
31 ; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v0, v1
32 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
[all …]
Durem.i32.ll12 ; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
18 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v3
21 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
22 ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v0, v1
23 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
24 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
25 ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v0, v1
26 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
27 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
34 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
[all …]
Dsdiv.i32.ll13 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
14 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v3
18 ; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v1
24 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
27 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4
28 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
29 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
30 ; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
32 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
33 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v4
[all …]
Dudiv.i32.ll12 ; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
18 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v3
21 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, 1, v2
22 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
23 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
24 ; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
26 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
27 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, 1, v2
28 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
29 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
[all …]
Dextractelement.i128.ll44 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, 16, v0
45 ; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
46 ; GFX8-NEXT: v_add_u32_e32 v10, vcc, 32, v0
47 ; GFX8-NEXT: v_addc_u32_e32 v11, vcc, 0, v1, vcc
50 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 48, v0
51 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
102 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v17
108 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
109 ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
110 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v16
[all …]
Dmul.ll215 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, s1, v0
228 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s1, v0
255 ; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v4
256 ; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v0
267 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4
268 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v0
296 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, s7, v0
305 ; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
306 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, s0, v2
308 ; GFX7-NEXT: v_add_i32_e32 v1, vcc, s8, v1
[all …]
Dextractelement.ll9 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
10 ; GCN-NEXT: v_cndmask_b32_e64 v6, 1.0, 2.0, vcc
12 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
13 ; GCN-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
14 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
15 ; GCN-NEXT: v_cndmask_b32_e64 v1, v1, 4.0, vcc
17 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
18 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
20 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
21 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
[all …]

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