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Searched refs:vmrg (Results 1 – 11 of 11) sorted by relevance

/external/llvm-project/llvm/test/MC/VE/
DVMRG.s6 # CHECK-INST: vmrg %v11, %s20, %v22
8 vmrg %v11, %s20, %v22 label
10 # CHECK-INST: vmrg %vix, %vix, %vix
12 vmrg.l %vix, %vix, %vix
14 # CHECK-INST: vmrg.w %vix, -64, %v22
16 vmrg.w %vix, -64, %v22
18 # CHECK-INST: vmrg %v11, 63, %v22, %vm11
20 vmrg.l %v11, 63, %v22, %vm11
22 # CHECK-INST: vmrg.w %v11, %v23, %v22, %vm12
24 vmrg.w %v11, %v23, %v22, %vm12
/external/llvm-project/llvm/test/CodeGen/VE/VELIntrinsics/
Dvmrg.ll15 ; CHECK-NEXT: vmrg %v0, %v0, %v1, %vm1
17 …%4 = tail call fast <256 x double> @llvm.ve.vl.vmrg.vvvml(<256 x double> %0, <256 x double> %1, <2…
22 declare <256 x double> @llvm.ve.vl.vmrg.vvvml(<256 x double>, <256 x double>, <256 x i1>, i32)
30 ; CHECK-NEXT: vmrg %v2, %v0, %v1, %vm1
35 …%5 = tail call fast <256 x double> @llvm.ve.vl.vmrg.vvvmvl(<256 x double> %0, <256 x double> %1, <…
40 declare <256 x double> @llvm.ve.vl.vmrg.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x d…
48 ; CHECK-NEXT: vmrg %v0, %s0, %v0, %vm1
50 …%4 = tail call fast <256 x double> @llvm.ve.vl.vmrg.vsvml(i64 %0, <256 x double> %1, <256 x i1> %2…
55 declare <256 x double> @llvm.ve.vl.vmrg.vsvml(i64, <256 x double>, <256 x i1>, i32)
63 ; CHECK-NEXT: vmrg %v1, %s0, %v0, %vm1
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dload-v4i8-improved.ll2 ; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
4 ; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s \
Dfma-mutate-register-constraint.ll5 ; CHECK-NOT: {{vmrg[hl]w.*(3[23456789]|[456][0-9])}}
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dload-v4i8-improved.ll3 ; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
6 ; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
Dfma-mutate-register-constraint.ll5 ; CHECK-NOT: {{vmrg[hl]w.*(3[23456789]|[456][0-9])}}
/external/llvm-project/llvm/lib/Target/VE/
DVEInstrVec.td1396 let cx = 0 in defm VMRG : RVm<"vmrg", 0xd6, V64, I64, VM>;
1397 // FIXME: vmrg.w should be called as pvmrg, but following assembly manual.
1398 let cx = 1 in defm VMRGW : RVm<"vmrg.w", 0xd6, V64, I64, VM512>;
1399 def : MnemonicAlias<"vmrg.l", "vmrg">;
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td911 // Match vmrg*(x,x)
925 // Match vmrg*(y,x), i.e., swapped operands. These fragments
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td965 // Match vmrg*(x,x)
979 // Match vmrg*(y,x), i.e., swapped operands. These fragments
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td997 // Match vmrg*(x,x)
1011 // Match vmrg*(y,x), i.e., swapped operands. These fragments
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4373 "gew\006vmrghb\006vmrghh\006vmrghw\006vmrglb\006vmrglh\006vmrglw\006vmrg"