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/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dvec_conv_fp32_to_i64_elts.ll48 ; CHECK-P8-NEXT: xxmrghw vs1, v2, v2
51 ; CHECK-P8-NEXT: xvcvspdp vs1, vs1
53 ; CHECK-P8-NEXT: xvcvdpuxds v3, vs1
54 ; CHECK-P8-NEXT: xxswapd vs1, v2
57 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
63 ; CHECK-P9-NEXT: xxmrghw vs1, v2, v2
65 ; CHECK-P9-NEXT: xvcvspdp vs1, vs1
67 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
68 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
75 ; CHECK-BE-NEXT: xxmrglw vs1, v2, v2
[all …]
Dvec_conv_fp_to_i_8byte_elts.ll36 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
38 ; CHECK-P8-NEXT: xvcvdpuxds vs1, vs1
41 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
47 ; CHECK-P9-NEXT: lxv vs1, 0(r4)
48 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
51 ; CHECK-P9-NEXT: stxv vs1, 0(r3)
57 ; CHECK-BE-NEXT: lxv vs1, 0(r4)
58 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
61 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
78 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
[all …]
Dvec_conv_i32_to_fp64_elts.ll48 ; CHECK-P8-NEXT: xvcvuxwdp vs1, v2
50 ; CHECK-P8-NEXT: xxswapd vs1, vs1
51 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
60 ; CHECK-P9-NEXT: xvcvuxwdp vs1, v2
61 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
70 ; CHECK-BE-NEXT: xvcvuxwdp vs1, v2
71 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
94 ; CHECK-P8-NEXT: xvcvuxwdp vs1, v2
98 ; CHECK-P8-NEXT: xxswapd vs1, vs1
100 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
[all …]
Dreduce_scalarization02.ll15 ; CHECK-NEXT: xxmrglw vs1, vs0, vs0
17 ; CHECK-NEXT: xvcvspdp vs1, vs1
19 ; CHECK-NEXT: stxv vs1, 0(r4)
26 ; CHECK-BE-NEXT: xxmrghw vs1, vs0, vs0
28 ; CHECK-BE-NEXT: xvcvspdp vs1, vs1
30 ; CHECK-BE-NEXT: stxv vs1, 0(r4)
50 ; CHECK-NEXT: xxmrglw vs1, vs0, vs0
52 ; CHECK-NEXT: xvcvspdp vs1, vs1
54 ; CHECK-NEXT: stxv vs1, 0(r4)
61 ; CHECK-BE-NEXT: xxmrghw vs1, vs0, vs0
[all …]
Dvec_conv_fp64_to_i32_elts.ll62 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
64 ; CHECK-P8-NEXT: xxswapd vs1, vs1
66 ; CHECK-P8-NEXT: xxmrgld vs2, vs0, vs1
67 ; CHECK-P8-NEXT: xxmrghd vs0, vs0, vs1
76 ; CHECK-P9-NEXT: lxv vs1, 16(r3)
77 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
78 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
87 ; CHECK-BE-NEXT: lxv vs1, 0(r3)
88 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
89 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
[all …]
Dvec_conv_fp32_to_i16_elts.ll18 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
19 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
36 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
38 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
173 ; CHECK-P8-NEXT: xxswapd vs1, v2
179 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
189 ; CHECK-P8-NEXT: xxsldwi vs1, v3, v3, 1
194 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
221 ; CHECK-P9-NEXT: lxv vs1, 0(r3)
223 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
[all …]
Dvec_conv_i_to_fp_4byte_elts.ll78 ; CHECK-P9-NEXT: lxv vs1, 0(r4)
79 ; CHECK-P9-NEXT: xvcvuxwsp vs1, vs1
82 ; CHECK-P9-NEXT: stxv vs1, 0(r3)
88 ; CHECK-BE-NEXT: lxv vs1, 0(r4)
89 ; CHECK-BE-NEXT: xvcvuxwsp vs1, vs1
92 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
124 ; CHECK-P9-NEXT: lxv vs1, 32(r4)
129 ; CHECK-P9-NEXT: xvcvuxwsp vs1, vs1
132 ; CHECK-P9-NEXT: stxv vs1, 32(r3)
140 ; CHECK-BE-NEXT: lxv vs1, 32(r4)
[all …]
Dvec_conv_fp_to_i_4byte_elts.ll78 ; CHECK-P9-NEXT: lxv vs1, 0(r4)
79 ; CHECK-P9-NEXT: xvcvspuxws vs1, vs1
82 ; CHECK-P9-NEXT: stxv vs1, 0(r3)
88 ; CHECK-BE-NEXT: lxv vs1, 0(r4)
89 ; CHECK-BE-NEXT: xvcvspuxws vs1, vs1
92 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
124 ; CHECK-P9-NEXT: lxv vs1, 32(r4)
129 ; CHECK-P9-NEXT: xvcvspuxws vs1, vs1
132 ; CHECK-P9-NEXT: stxv vs1, 32(r3)
140 ; CHECK-BE-NEXT: lxv vs1, 32(r4)
[all …]
Dvec_conv_i_to_fp_8byte_elts.ll36 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
38 ; CHECK-P8-NEXT: xvcvuxddp vs1, vs1
41 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
49 ; CHECK-P9-NEXT: xvcvuxddp vs1, v2
50 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
59 ; CHECK-BE-NEXT: xvcvuxddp vs1, v2
60 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
78 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
82 ; CHECK-P8-NEXT: xvcvuxddp vs1, vs1
85 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
[all …]
Dmma-acc-memops.ll15 ; LE-PAIRED-NEXT: plxv vs1, f@PCREL+96(0), 1
20 ; LE-PAIRED-NEXT: pstxv vs1, f@PCREL+160(0), 1
29 ; BE-PAIRED-NEXT: lxv vs1, 80(r3)
33 ; BE-PAIRED-NEXT: stxv vs1, 144(r3)
52 ; LE-PAIRED-NEXT: lxv vs1, 32(r6)
60 ; LE-PAIRED-NEXT: stxv vs1, 32(r3)
72 ; BE-PAIRED-NEXT: lxv vs1, 16(r6)
77 ; BE-PAIRED-NEXT: stxv vs1, 16(r3)
92 ; LE-PAIRED-NEXT: plxv vs1, f@PCREL+43(0), 1
97 ; LE-PAIRED-NEXT: pstxv vs1, f@PCREL+51(0), 1
[all …]
Dmma-outer-product.ll22 ; CHECK-NEXT: xxlor vs1, v1, v1
32 ; CHECK-NEXT: stxv vs1, 32(r3)
47 ; CHECK-BE-NEXT: xxlor vs1, v1, v1
56 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
82 ; CHECK-NEXT: xxlor vs1, vs5, vs5
94 ; CHECK-NEXT: stxv vs1, 0(r5)
106 ; CHECK-BE-NEXT: xxlor vs1, vs5, vs5
117 ; CHECK-BE-NEXT: stxv vs1, 0(r4)
150 ; CHECK-NEXT: stxv vs1, 32(r7)
159 ; CHECK-BE-NEXT: stxv vs1, 16(r7)
[all …]
Dvec_conv_fp32_to_i8_elts.ll18 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
19 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
39 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
41 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
182 ; CHECK-P8-NEXT: xxswapd vs1, v2
188 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
198 ; CHECK-P8-NEXT: xxsldwi vs1, v3, v3, 1
203 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
232 ; CHECK-P9-NEXT: lxv vs1, 0(r3)
234 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
[all …]
Dvsx_insert_extract_le.ll20 ; CHECK-NEXT: xxmrghd v2, vs0, vs1
28 ; CHECK-P9-VECTOR-NEXT: xxmrghd v2, vs0, vs1
35 ; CHECK-P9-NEXT: xxswapd vs1, f1
36 ; CHECK-P9-NEXT: xxpermdi v2, vs0, vs1, 1
52 ; CHECK-NEXT: xxpermdi v2, vs1, vs0, 1
60 ; CHECK-P9-VECTOR-NEXT: xxpermdi v2, vs1, vs0, 1
67 ; CHECK-P9-NEXT: xxswapd vs1, f1
68 ; CHECK-P9-NEXT: xxmrgld v2, vs1, vs0
81 ; CHECK-NEXT: lxvd2x vs1, 0, r3
87 ; CHECK-P9-VECTOR-NEXT: lxvd2x vs1, 0, r3
[all …]
Dmma-integer-based-outer-product.ll16 ; CHECK-NEXT: stxv vs1, 32(r7)
25 ; CHECK-BE-NEXT: stxv vs1, 16(r7)
47 ; CHECK-NEXT: stxv vs1, 32(r7)
56 ; CHECK-BE-NEXT: stxv vs1, 16(r7)
75 ; CHECK-NEXT: lxv vs1, 32(r3)
83 ; CHECK-NEXT: stxv vs1, 32(r7)
90 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
97 ; CHECK-BE-NEXT: stxv vs1, 16(r7)
118 ; CHECK-NEXT: lxv vs1, 32(r3)
126 ; CHECK-NEXT: stxv vs1, 32(r7)
[all …]
Dbfloat16-outer-product.ll16 ; CHECK-NEXT: stxv vs1, 32(r7)
25 ; CHECK-BE-NEXT: stxv vs1, 16(r7)
47 ; CHECK-NEXT: stxv vs1, 32(r7)
56 ; CHECK-BE-NEXT: stxv vs1, 16(r7)
75 ; CHECK-NEXT: lxv vs1, 32(r3)
83 ; CHECK-NEXT: stxv vs1, 32(r7)
90 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
97 ; CHECK-BE-NEXT: stxv vs1, 16(r7)
118 ; CHECK-NEXT: lxv vs1, 32(r3)
126 ; CHECK-NEXT: stxv vs1, 32(r7)
[all …]
Dvec_conv_i64_to_fp32_elts.ll16 ; CHECK-P8-NEXT: xxlor vs1, v2, v2
19 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
21 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3
45 ; CHECK-BE-NEXT: xxlor vs1, v2, v2
63 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
65 ; CHECK-P8-NEXT: xxswapd v3, vs1
67 ; CHECK-P8-NEXT: xvcvuxdsp vs1, v3
69 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3
109 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
113 ; CHECK-P8-NEXT: xxswapd v3, vs1
[all …]
Dmma-intrinsics.ll16 ; CHECK-NEXT: xxlor vs1, v3, v3
20 ; CHECK-NEXT: stxv vs1, 32(r3)
29 ; CHECK-BE-NEXT: xxlor vs1, v3, v3
32 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
72 ; CHECK-NEXT: xxlor vs1, v3, v3
77 ; CHECK-NEXT: stxv vs1, 32(r3)
86 ; CHECK-BE-NEXT: xxlor vs1, v3, v3
90 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
111 ; CHECK-NEXT: xxlor vs1, v3, v3
115 ; CHECK-NEXT: stxv vs1, 32(r3)
[all …]
Duint-to-fp-v4i32.ll27 ; P9BE-NEXT: xxmrghd v2, vs0, vs1
42 ; P9LE-NEXT: xxmrghd v2, vs1, vs0
56 ; P8BE-NEXT: xxmrghd v2, vs0, vs1
71 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
90 ; P9BE-NEXT: xxmrghd v2, vs0, vs1
99 ; P9LE-NEXT: xxmrghd v2, vs1, vs0
111 ; P8BE-NEXT: xxmrghd v2, vs0, vs1
117 ; P8LE-NEXT: xxsldwi vs1, v3, v3, 1
124 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
Dvec-itofp.ll36 ; CHECK-P8-NEXT: xvcvuxddp vs1, v5
40 ; CHECK-P8-NEXT: xxswapd vs1, vs1
45 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
66 ; CHECK-P9-NEXT: xvcvuxddp vs1, v3
71 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
96 ; CHECK-BE-NEXT: xvcvuxddp vs1, v3
101 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
131 ; CHECK-P8-NEXT: xvcvuxddp vs1, v3
133 ; CHECK-P8-NEXT: xxswapd vs1, vs1
134 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
[all …]
Dvec_conv_fp64_to_i16_elts.ll67 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
71 ; CHECK-P8-NEXT: xxswapd vs1, vs1
91 ; CHECK-P9-NEXT: lxv vs1, 0(r3)
94 ; CHECK-P9-NEXT: xxswapd vs1, vs1
115 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
118 ; CHECK-BE-NEXT: xxswapd vs1, vs1
152 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
160 ; CHECK-P8-NEXT: xxswapd vs1, vs1
199 ; CHECK-P9-NEXT: lxv vs1, 32(r3)
215 ; CHECK-P9-NEXT: xxswapd vs1, vs1
[all …]
/external/rust/crates/libz-sys/src/zlib-ng/arch/power/
Dadler32_power8.c78 vector unsigned int vs1 = { 0 }; in adler32_power8() local
85 vs1[0] = s1; in adler32_power8()
98 vs1_save = vec_add(vs1_save, vs1); in adler32_power8()
100 vs1 = vec_add(vsum1, vs1); in adler32_power8()
106 vs1 = vec_sumsu(vs1, vsum1); in adler32_power8()
112 vs1[0] = vs1[0] % BASE; in adler32_power8()
117 vs1 = vec_and(vs1, vmask); in adler32_power8()
133 vs1_save = vec_add(vs1_save, vs1); in adler32_power8()
135 vs1 = vec_add(vsum1, vs1); in adler32_power8()
141 vs1 = vec_sumsu(vs1, vsum1); in adler32_power8()
[all …]
/external/rust/crates/libz-sys/src/zlib-ng/arch/x86/
Dadler32_ssse3.c55 __m128i vs1 = _mm_load_si128((__m128i*)s1); in adler32_ssse3() local
57 __m128i vs1_0 = vs1; in adler32_ssse3()
80 vs1 = _mm_add_epi32(vsum1, vs1); in adler32_ssse3()
85 vs1_0 = vs1; in adler32_ssse3()
94 _mm_store_si128((__m128i*)s1_unpack, vs1); in adler32_ssse3()
Dadler32_avx.c58 __m256i vs1 = _mm256_load_si256((__m256i*)s1); in adler32_avx2() local
60 __m256i vs1_0 = vs1; in adler32_avx2()
78 vs1 = _mm256_add_epi32(vsum1, vs1); in adler32_avx2()
83 vs1_0 = vs1; in adler32_avx2()
91 _mm256_store_si256((__m256i*)s1_unpack, vs1); in adler32_avx2()
/external/XNNPACK/src/f32-velu/gen/
Dvelu-scalar-rr2-lut16-p3-x2.c64 float vs1 = fp32_from_bits(xnn_table_exp2minus_k_over_16[vidx1] + ven1); in xnn_f32_velu_ukernel__scalar_rr2_lut16_p3_x2() local
73 vs1 = 0.0f; in xnn_f32_velu_ukernel__scalar_rr2_lut16_p3_x2()
85 vt1 *= vs1; in xnn_f32_velu_ukernel__scalar_rr2_lut16_p3_x2()
86 vs1 -= vone; in xnn_f32_velu_ukernel__scalar_rr2_lut16_p3_x2()
93 const float ve1 = (vp1 + vs1) * valpha; in xnn_f32_velu_ukernel__scalar_rr2_lut16_p3_x2()
Dvelu-scalar-rr2-p6-x2.c56 float vs1 = fp32_from_bits(fp32_to_bits(vn1) << 23); in xnn_f32_velu_ukernel__scalar_rr2_p6_x2() local
70 vs1 = 0.0f; in xnn_f32_velu_ukernel__scalar_rr2_p6_x2()
91 vt1 *= vs1; in xnn_f32_velu_ukernel__scalar_rr2_p6_x2()
92 vs1 -= vone; in xnn_f32_velu_ukernel__scalar_rr2_p6_x2()
99 const float ve1 = (vp1 + vs1) * valpha; in xnn_f32_velu_ukernel__scalar_rr2_p6_x2()

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