Searched refs:vshlc (Results 1 – 7 of 7) sorted by relevance
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/ |
D | vshlc.ll | 8 ; CHECK-NEXT: vshlc q0, r1, #18 13 %1 = tail call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %a, i32 %0, i32 18) 24 ; CHECK-NEXT: vshlc q0, r1, #16 29 %1 = tail call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %a, i32 %0, i32 16) 40 ; CHECK-NEXT: vshlc q0, r1, #4 45 %1 = tail call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %a, i32 %0, i32 4) 56 ; CHECK-NEXT: vshlc q0, r1, #17 61 %1 = tail call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %a, i32 %0, i32 17) 72 ; CHECK-NEXT: vshlc q0, r1, #17 77 %1 = tail call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %a, i32 %0, i32 17) [all …]
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/external/llvm-project/llvm/test/MC/ARM/ |
D | mve-shifts.s | 7 # CHECK: vshlc q0, lr, #8 @ encoding: [0xa8,0xee,0xce,0x0f] 8 # CHECK-NOFP: vshlc q0, lr, #8 @ encoding: [0xa8,0xee,0xce,0x0f] 9 vshlc q0, lr, #8 label 12 vshlc q0, lr, #33 label
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/external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
D | mve-shifts.txt | 5 # CHECK: vshlc q0, lr, #8 @ encoding: [0xa8,0xee,0xce,0x0f]
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/external/llvm-project/clang/include/clang/Basic/ |
D | arm_mve.td | 1305 (IRInt<"vshlc", [Vector]> $v, $s, $imm):$pair,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMInstrMVE.td | 2308 NoItinerary, "vshlc", "", "$QdSrc, $RdmSrc, $imm",
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/external/llvm-project/llvm/lib/Target/ARM/ |
D | ARMInstrMVE.td | 2676 NoItinerary, "vshlc", "", "$QdSrc, $RdmSrc, $imm",
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
D | ARMGenAsmMatcher.inc | 14530 …{ 3698 /* vshlc */, ARM::MVE_VSHLC, Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__…
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