/external/llvm-project/llvm/test/CodeGen/Mips/ |
D | bswap.ll | 13 ; MIPS32: wsbh $[[R0:[0-9]+]] 17 ; MM: wsbh $[[R0:[0-9]+]] 21 ; MIPS64: wsbh $[[R0:[0-9]+]] 44 ; MIPS32: wsbh $[[R0:[0-9]+]] 46 ; MIPS32: wsbh $[[R0:[0-9]+]] 50 ; MM: wsbh $[[R0:[0-9]+]] 52 ; MM: wsbh $[[R0:[0-9]+]] 88 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]] 90 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]] 92 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]] [all …]
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/external/llvm/test/CodeGen/Mips/ |
D | bswap.ll | 8 ; MIPS32: wsbh $[[R0:[0-9]+]] 12 ; MIPS64: wsbh $[[R0:[0-9]+]] 35 ; MIPS32: wsbh $[[R0:[0-9]+]] 37 ; MIPS32: wsbh $[[R0:[0-9]+]] 75 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]] 77 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]] 79 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]] 81 ; MIPS32-DAG: wsbh $[[R0:[0-9]+]] 85 ; MIPS64-DAG: wsbh $[[R0:[0-9]+]] 87 ; MIPS64-DAG: wsbh $[[R0:[0-9]+]] [all …]
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/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ |
D | bswap.ll | 23 ; MIPS32R2-NEXT: wsbh $1, $4 59 ; MIPS32R2-NEXT: wsbh $1, $5 61 ; MIPS32R2-NEXT: wsbh $1, $4
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D | bitreverse.ll | 44 ; MIPS32R2-NEXT: wsbh $1, $4 139 ; MIPS32R2-NEXT: wsbh $2, $5 162 ; MIPS32R2-NEXT: wsbh $1, $1
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/external/llvm-project/llvm/test/CodeGen/Mips/Fast-ISel/ |
D | bswap1.ll | 27 ; 32R2: wsbh $[[RESULT:[0-9]+]], $[[A_VAL]] 51 ; 32R2: wsbh $[[TMP:[0-9]+]], $[[B_VAL]]
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/external/llvm/test/CodeGen/Mips/Fast-ISel/ |
D | bswap1.ll | 27 ; 32R2: wsbh $[[RESULT:[0-9]+]], $[[A_VAL]] 51 ; 32R2: wsbh $[[TMP:[0-9]+]], $[[B_VAL]]
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/external/llvm-project/llvm/test/MC/Mips/ |
D | mips64-alu-instructions.s | 33 # CHECK: wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c] 61 wsbh $6, $7
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D | mips-alu-instructions.s | 36 # CHECK: wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c] 67 wsbh $6, $7
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/external/llvm/test/MC/Mips/ |
D | mips-alu-instructions.s | 36 # CHECK: wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c] 67 wsbh $6, $7
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D | mips64-alu-instructions.s | 33 # CHECK: wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c] 61 wsbh $6, $7
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/external/capstone/suite/MC/Mips/ |
D | mips64-alu-instructions.s.cs | 28 0xa0,0x30,0x07,0x7c = wsbh $a2, $a3
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D | mips-alu-instructions.s.cs | 31 0xa0,0x30,0x07,0x7c = wsbh $a2, $a3
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/external/llvm/test/MC/Mips/mips4/ |
D | invalid-mips64r2.s | 33 …wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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/external/llvm-project/llvm/test/MC/Mips/mips64/ |
D | invalid-mips64r2.s | 31 …wsbh $k1,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/external/llvm/test/MC/Mips/mips64/ |
D | invalid-mips64r2.s | 31 …wsbh $k1,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/external/llvm-project/llvm/test/MC/Mips/mips4/ |
D | invalid-mips64r2.s | 33 …wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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/external/llvm/test/MC/Mips/mips5/ |
D | invalid-mips64r2.s | 39 …wsbh $k1,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/external/llvm-project/llvm/test/MC/Mips/mips5/ |
D | invalid-mips64r2.s | 39 …wsbh $k1,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/external/llvm/test/MC/Mips/mips32/ |
D | invalid-mips32r2.s | 36 …wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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/external/llvm-project/llvm/test/MC/Mips/mips32/ |
D | invalid-mips32r2.s | 36 …wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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/external/llvm/test/MC/Mips/mips2/ |
D | invalid-mips32r2.s | 68 …wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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/external/llvm-project/llvm/test/MC/Mips/micromips/ |
D | valid.s | 231 wsbh $9, $6 # CHECK: wsbh $9, $6 # encoding: [0x01,0x26,0x7b,0x3c] label
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/external/llvm/test/MC/Mips/micromips32r6/ |
D | invalid.s | 75 wsbh $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 76 wsbh $3, $33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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D | valid.s | 123 wsbh $3, $4 # CHECK: wsbh $3, $4 # encoding: [0x00,0x64,0x7b,0x3c]
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/external/llvm/test/MC/Mips/micromips64r6/ |
D | valid.s | 141 wsbh $3, $4 # CHECK: wsbh $3, $4 # encoding: [0x00,0x64,0x7b,0x3c]
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