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/external/llvm-project/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt40 0x10 0x43 0x23 0x0e
43 0x10 0x43 0x21 0x8e
46 0x10 0x43 0x21 0x0e
49 0x10 0x43 0x21 0xce
52 0x10 0x43 0x21 0x4e
55 0x10 0x43 0x20 0x0e
58 0x10 0x43 0x20 0x8e
61 0x10 0x43 0x20 0x4e
64 0x10 0x43 0x20 0xce
67 0x10 0x40 0x1b 0x4e
[all …]
Dppc64-encoding-ISA31.txt38 0x07 0x90 0x80 0x44 0xec 0x01 0x10 0x98
41 0x07 0x90 0x80 0x44 0xec 0x01 0x10 0x90
53 0x07 0x90 0x00 0x44 0xec 0x01 0x10 0xd8
56 0x07 0x90 0x00 0x44 0xec 0x01 0x10 0xd0
86 0x07 0x90 0x04 0x44 0xec 0x01 0x11 0x10
89 0x07 0x90 0x40 0x44 0xec 0x01 0x10 0x18
92 0x07 0x90 0x40 0x44 0xec 0x01 0x10 0x10
101 0xec 0x01 0x10 0x98
104 0xec 0x01 0x10 0x90
116 0xec 0x01 0x10 0xd8
[all …]
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt40 0x10 0x43 0x23 0x0e
43 0x10 0x43 0x21 0x8e
46 0x10 0x43 0x21 0x0e
49 0x10 0x43 0x21 0xce
52 0x10 0x43 0x21 0x4e
55 0x10 0x43 0x20 0x0e
58 0x10 0x43 0x20 0x8e
61 0x10 0x43 0x20 0x4e
64 0x10 0x43 0x20 0xce
67 0x10 0x40 0x1b 0x4e
[all …]
Dqpx.txt4 0x10 0x60 0x2a 0x10
7 0x10 0x64 0x28 0x2a
13 0x10 0x64 0x2a 0x08
16 0x10 0x64 0x28 0x88
19 0x10 0x60 0x2e 0x9c
25 0x10 0x60 0x2f 0x9c
31 0x10 0x63 0x18 0x08
34 0x10 0x64 0x28 0x10
37 0x10 0x64 0x22 0x88
40 0x10 0x60 0x2e 0x5c
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Darm-vmrs_vmsr.txt8 [0x10,0xfa,0xf1,0xee]
9 [0x10,0xfa,0xf1,0xee]
10 [0x10,0xfa,0xf1,0xee]
11 [0x10,0xaa,0xf1,0xee]
12 [0x10,0x2a,0xf0,0xee]
13 [0x10,0x3a,0xf0,0xee]
14 [0x10,0x4a,0xf7,0xee]
15 [0x10,0x5a,0xf6,0xee]
16 [0x10,0x6a,0xf5,0xee]
17 [0x10,0xda,0xf1,0xee]
[all …]
Dthumb-vmrs_vmsr.txt16 [0xf1,0xee,0x10,0xfa]
17 [0xf1,0xee,0x10,0xfa]
18 [0xf1,0xee,0x10,0xfa]
19 [0xf1,0xee,0x10,0xaa]
20 [0xf0,0xee,0x10,0x2a]
21 [0xf0,0xee,0x10,0x3a]
22 [0xf7,0xee,0x10,0x4a]
23 [0xf6,0xee,0x10,0x5a]
24 [0xf5,0xee,0x10,0x6a]
25 [0xf1,0xee,0x10,0xda]
[all …]
Dthumbv8.1m-vmrs-vmsr.txt18 # CHECK-NOVFP: vmsr fpscr_nzcvqc, r0 @ encoding: [0xe2,0xee,0x10,0x0a]
19 # CHECK-NOMVE: vmsr fpscr_nzcvqc, r0 @ encoding: [0xe2,0xee,0x10,0x0a]
20 # CHECK-NOSEC: vmsr fpscr_nzcvqc, r0 @ encoding: [0xe2,0xee,0x10,0x0a]
21 # CHECK: vmsr fpscr_nzcvqc, r0 @ encoding: [0xe2,0xee,0x10,0x0a]
22 [0xe2,0xee,0x10,0x0a]
26 # CHECK-NOVFP: vmrs r10, fpscr_nzcvqc @ encoding: [0xf2,0xee,0x10,0xaa]
27 # CHECK-NOMVE: vmrs r10, fpscr_nzcvqc @ encoding: [0xf2,0xee,0x10,0xaa]
28 # CHECK-NOSEC: vmrs r10, fpscr_nzcvqc @ encoding: [0xf2,0xee,0x10,0xaa]
29 # CHECK: vmrs r10, fpscr_nzcvqc @ encoding: [0xf2,0xee,0x10,0xaa]
30 [0xf2,0xee,0x10,0xaa]
[all …]
Dvmrs-vmsr-invalid.txt5 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
9 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
13 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
17 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
21 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
25 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
29 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
33 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
37 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
41 # CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
[all …]
Dunpredictable-AI1cmp-arm.txt4 # CHECK: 0x01 0x10 0x50 0x03
5 0x01 0x10 0x50 0x03
8 # CHECK: 0x82 0x10 0x50 0x01
9 0x82 0x10 0x50 0x01
12 # CHECK: 0x02 0x10 0x50 0x01
13 0x02 0x10 0x50 0x01
20 # CHECK: 0x10 0x11 0x52 0x01
21 0x10 0x11 0x52 0x01
24 # CHECK: 0x10 0x0f 0x51 0x01
25 0x10 0x0f 0x51 0x01
[all …]
/external/llvm-project/llvm/test/MC/RISCV/
Dnumeric-reg-names.s7 # CHECK-NUMERIC: addi x10, x0, 1
8 # CHECK-NUMERIC-NEXT: addi x10, x0, 1
12 # CHECK-NUMERIC: addi x10, x1, 1
13 # CHECK-NUMERIC-NEXT: addi x10, x1, 1
17 # CHECK-NUMERIC: addi x10, x2, 1
18 # CHECK-NUMERIC-NEXT: addi x10, x2, 1
22 # CHECK-NUMERIC: addi x10, x3, 1
23 # CHECK-NUMERIC-NEXT: addi x10, x3, 1
27 # CHECK-NUMERIC: addi x10, x4, 1
28 # CHECK-NUMERIC-NEXT: addi x10, x4, 1
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Daarch64-ldst-modified-baseReg.mir9 # ldr x9 [x10]
10 # ldr x10 [x8]
11 # ldr x10 [x10, 8],
12 # the first and third ldr instructions cannot be converted to ldp x9, x10, [x10].
16 # CHECK: $x9 = LDRXui $x10, 1 :: (load 8)
17 # CHECK: $x10 = LDURXi $x8, 1 :: (load 8)
18 # CHECK: $x10 = LDRXui $x10, 0 :: (load 8)
25 liveins: $x8, $x10
27 $x9 = LDRXui $x10, 1 :: (load 8)
28 $x10 = LDURXi $x8, 1 :: (load 8)
[all …]
Di128_volatile_load_store.ll12 ; CHECK-NEXT: adrp x10, y
13 ; CHECK-NEXT: add x10, x10, :lo12:y
14 ; CHECK-NEXT: stp x8, x9, [x10]
27 ; CHECK-NEXT: adrp x10, y
28 ; CHECK-NEXT: add x10, x10, :lo12:y
29 ; CHECK-NEXT: stp x8, x9, [x10, #504]
43 ; CHECK-NEXT: adrp x10, y
44 ; CHECK-NEXT: add x10, x10, :lo12:y
45 ; CHECK-NEXT: add x10, x10, #512 // =512
46 ; CHECK-NEXT: stp x8, x9, [x10]
[all …]
Dsve-split-extract-elt.ll28 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00…
30 ; CHECK-NEXT: rdvl x10, #2
33 ; CHECK-NEXT: sub x10, x10, #1 // =1
36 ; CHECK-NEXT: cmp x9, x10
39 ; CHECK-NEXT: csel x9, x9, x10, lo
53 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00…
55 ; CHECK-NEXT: rdvl x10, #1
58 ; CHECK-NEXT: sub x10, x10, #1 // =1
61 ; CHECK-NEXT: cmp x9, x10
64 ; CHECK-NEXT: csel x9, x9, x10, lo
[all …]
/external/bouncycastle/repackaged/bcprov/src/main/java/com/android/org/bouncycastle/crypto/engines/
DRC2Engine.java212 int x76, x54, x32, x10; in encryptBlock() local
217 x10 = ((in[inOff + 1] & 0xff) << 8) + (in[inOff + 0] & 0xff); in encryptBlock()
221 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
222 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
223 x54 = rotateWordLeft(x54 + (x76 & ~x32) + (x10 & x32) + workingKey[i+2], 3); in encryptBlock()
224 x76 = rotateWordLeft(x76 + (x10 & ~x54) + (x32 & x54) + workingKey[i+3], 5); in encryptBlock()
227 x10 += workingKey[x76 & 63]; in encryptBlock()
228 x32 += workingKey[x10 & 63]; in encryptBlock()
234 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
235 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
[all …]
/external/bouncycastle/bcprov/src/main/java/org/bouncycastle/crypto/engines/
DRC2Engine.java210 int x76, x54, x32, x10; in encryptBlock() local
215 x10 = ((in[inOff + 1] & 0xff) << 8) + (in[inOff + 0] & 0xff); in encryptBlock()
219 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
220 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
221 x54 = rotateWordLeft(x54 + (x76 & ~x32) + (x10 & x32) + workingKey[i+2], 3); in encryptBlock()
222 x76 = rotateWordLeft(x76 + (x10 & ~x54) + (x32 & x54) + workingKey[i+3], 5); in encryptBlock()
225 x10 += workingKey[x76 & 63]; in encryptBlock()
226 x32 += workingKey[x10 & 63]; in encryptBlock()
232 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
233 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
[all …]
/external/bouncycastle/repackaged_platform/bcprov/src/main/java/com/android/internal/org/bouncycastle/crypto/engines/
DRC2Engine.java212 int x76, x54, x32, x10; in encryptBlock() local
217 x10 = ((in[inOff + 1] & 0xff) << 8) + (in[inOff + 0] & 0xff); in encryptBlock()
221 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
222 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
223 x54 = rotateWordLeft(x54 + (x76 & ~x32) + (x10 & x32) + workingKey[i+2], 3); in encryptBlock()
224 x76 = rotateWordLeft(x76 + (x10 & ~x54) + (x32 & x54) + workingKey[i+3], 5); in encryptBlock()
227 x10 += workingKey[x76 & 63]; in encryptBlock()
228 x32 += workingKey[x10 & 63]; in encryptBlock()
234 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
235 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dgfx10_mimg.txt9 # GFX10: image_load v[252:255], v[2:4], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm ; encoding: [0x10…
10 0x10,0x1f,0x00,0xf0,0x02,0xfc,0x00,0x00
27 …], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x1f,0x04,0xf0,0x08,0x10,0x01,0x00]
28 0x00,0x1f,0x04,0xf0,0x08,0x10,0x01,0x00
30 …], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ; encoding: [0x08,0x1f,0x08,0xf0,0x08,0x10,0x01,0x00]
31 0x08,0x1f,0x08,0xf0,0x08,0x10,0x01,0x00
33 …[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm glc ; encoding: [0x08,0x3f,0x0c,0xf0,0x08,0x10,0x01,0x00]
34 0x08,0x3f,0x0c,0xf0,0x08,0x10,0x01,0x00
36 …[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm slc ; encoding: [0x08,0x1f,0x10,0xf2,0x08,0x10,0x01,0x00]
37 0x08,0x1f,0x10,0xf2,0x08,0x10,0x01,0x00
[all …]
/external/llvm-project/llvm/test/CodeGen/RISCV/
Dmachineoutliner.mir29 liveins: $x10, $x11
36 $x12 = ADDI $x10, 17
38 $x10 = SUB $x10, $x11
39 PseudoRET implicit $x10
47 liveins: $x10, $x11
54 $x12 = ADDI $x10, 17
56 $x10 = SUB $x10, $x11
57 PseudoRET implicit $x10
65 liveins: $x10, $x11
72 $x12 = ADDI $x10, 17
[all …]
/external/scapy/test/
Dcan.uts34 …x10\x00\x00\x00\x10\x00\x00\x00\x00\x00\x06B\x08\x7f\x00\x00@\x08\x10\x00\x00\x00\x00\x00\xf8\xf3m…
/external/capstone/bindings/ocaml/
Dtest_m680x.ml27 let _M6800_CODE = "\x01\x09\x36\x64\x7f\x74\x10\x00\x90\x10\xA4\x10\xb6\x10\x00\x39";;
28 let _M6801_CODE = "\x04\x05\x3c\x3d\x38\x93\x10\xec\x10\xed\x10\x39";;
29 …00\x17\x22\x28\x00\x2e\x00\x40\x42\x5a\x70\x8e\x97\x9c\xa0\x15\xad\x00\xc3\x10\x00\xda\x12\x34\xe5…
30 …45\x10\x00\x4b\x00\x51\x10\x52\x5e\x22\x62\x65\x12\x34\x72\x84\x85\x86\x87\x8a\x8b\x8c\x94\x95\xa7…
31 let _HD6301_CODE = "\x6b\x10\x00\x71\x10\x00\x72\x10\x10\x39";;
32 …x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa…
33 …x10\x10\x62\x10\x10\x7b\x10\x10\x00\xcd\x49\x96\x02\xd2\x10\x30\x23\x10\x38\x10\x3b\x10\x53\x10\x5…
34 …x10\x00\x13\x99\x08\x00\x14\x7f\x02\x15\x7f\x01\x1e\x7f\x20\x00\x8f\xcf\x18\x08\x18\x30\x18\x3c\x1…
35 …x10\x00\x80\x00\x3b\x4a\x10\x00\x04\x4b\x01\x04\x4f\x7f\x80\x00\x8f\x10\x00\xb7\x52\xb7\xb1\xa6\x6…
36 let _HCS08_CODE = "\x32\x10\x00\x9e\xae\x9e\xce\x7f\x9e\xbe\x10\x00\x9e\xfe\x7f\x3e\x10\x00\x9e\xf3…
/external/libhevc/common/arm64/
Dihevc_intra_pred_luma_mode_18_34.s121 mov x10,x2
159 st1 {v0.8b},[x10],x3
160 st1 {v1.8b},[x10],x3
162 st1 {v2.8b},[x10],x3
165 st1 {v3.8b},[x10],x3
168 st1 {v4.8b},[x10],x3
170 st1 {v5.8b},[x10],x3
172 st1 {v6.8b},[x10],x3
174 st1 {v7.8b},[x10],x3
177 sub x20,x10,x14
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dunpredictable-AI1cmp-arm.txt4 # CHECK: 0x01 0x10 0x50 0x03
5 0x01 0x10 0x50 0x03
8 # CHECK: 0x82 0x10 0x50 0x01
9 0x82 0x10 0x50 0x01
12 # CHECK: 0x02 0x10 0x50 0x01
13 0x02 0x10 0x50 0x01
20 # CHECK: 0x10 0x11 0x52 0x01
21 0x10 0x11 0x52 0x01
24 # CHECK: 0x10 0x0f 0x51 0x01
25 0x10 0x0f 0x51 0x01
[all …]
/external/rust/crates/ring/pregenerated/
Decp_nistz256-armv8-ios64.S84 ldp x10,x11,[x2,#16]
129 umulh x10,x6,x3
139 adcs x17,x17,x10
142 subs x10,x14,x8 // "*0xffff0001"
148 adcs x16,x17,x10 // +=acc[0]*0xffff0001
149 mul x10,x6,x3 // lo(a[2]*b[i])
158 adcs x16,x16,x10
159 umulh x10,x6,x3 // hi(a[2]*b[i])
168 adcs x17,x17,x10
171 subs x10,x14,x8 // "*0xffff0001"
[all …]
Decp_nistz256-armv8-linux64.S85 ldp x10,x11,[x2,#16]
130 umulh x10,x6,x3
140 adcs x17,x17,x10
143 subs x10,x14,x8 // "*0xffff0001"
149 adcs x16,x17,x10 // +=acc[0]*0xffff0001
150 mul x10,x6,x3 // lo(a[2]*b[i])
159 adcs x16,x16,x10
160 umulh x10,x6,x3 // hi(a[2]*b[i])
169 adcs x17,x17,x10
172 subs x10,x14,x8 // "*0xffff0001"
[all …]
/external/arm-trusted-firmware/lib/el3_runtime/aarch64/
Dcontext.S49 mrs x10, afsr0_el2
50 stp x9, x10, [x0, #CTX_ACTLR_EL2]
70 mrs x10, dbgvcr32_el2
71 stp x10, x11, [x0, #CTX_DBGVCR32_EL2]
85 mrs x10, hstr_el2
86 stp x9, x10, [x0, #CTX_HPFAR_EL2]
108 mrs x10, sp_el2
110 stp x10, x11, [x0, #CTX_SP_EL2]
128 mrs x10, TFSR_EL2
129 str x10, [x0, #CTX_TFSR_EL2]
[all …]

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