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/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc12749 ZRegister zd_lsl = z27.WithLaneSize(lane_size_in_bits); in BitwiseShiftImmHelper() local
12756 __ Lsl(zd_lsl, zn, shift - 1); // Lsl supports 0 - lane_size-1. in BitwiseShiftImmHelper()
12791 if (!core.HasSVELane(zd_lsl, lane)) break; in BitwiseShiftImmHelper()
12794 ASSERT_EQUAL_SVE_LANE(result & mask, zd_lsl, lane); in BitwiseShiftImmHelper()