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/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc12748 ZRegister zd_lsr = z26.WithLaneSize(lane_size_in_bits); in BitwiseShiftImmHelper() local
12755 __ Lsr(zd_lsr, zn, shift); in BitwiseShiftImmHelper()
12783 if (!core.HasSVELane(zd_lsr, lane)) break; in BitwiseShiftImmHelper()
12786 ASSERT_EQUAL_SVE_LANE(result, zd_lsr, lane); in BitwiseShiftImmHelper()