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Searched refs:zeroing (Results 1 – 25 of 98) sorted by relevance

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/external/python/cpython2/Mac/Demo/applescript/Disk_Copy/
DStandard_Suite.py150 class zeroing(aetools.NProperty): class
324 'zeroing' : zeroing,
454 'PZeB' : zeroing,
/external/llvm/test/CodeGen/X86/
DTruncAssertZext.ll2 ; Checks that a zeroing mov is inserted for the trunc/zext pair even when
D2012-12-06-python27-miscompile.ll6 ; Make sure that we are zeroing one memory location at a time using xorl and
/external/llvm-project/llvm/test/CodeGen/X86/
DTruncAssertSext.ll3 ; Checks that a zeroing mov is inserted for the trunc/zext pair even when
Dmerge-consecutive-stores.ll4 ; Make sure that we are zeroing one memory location at a time using xorl and
DTruncAssertZext.ll3 ; Checks that a zeroing mov is inserted for the trunc/zext pair even when
Dmisched_phys_reg_assign_order.ll6 ; PR39391 - The load of %v1 should be scheduled before the zeroing of the A-D registers.
/external/pigweed/pw_persistent_ram/
Ddocs.rst80 after zeroing. Alternatively containers can be individually cleared.
97 4. Consider zeroing persistent RAM to recover from crashes which may be induced
99 5. Consider zeroing persistent RAM on cold boots to always start from a
/external/e2fsprogs/doc/RelNotes/
Dv1.11.txt41 Fixed bug in ext2fs_resize_generic_bitmap; it had not be zeroing all
/external/llvm/test/CodeGen/AArch64/
Darm64-zero-cycle-zeroing.ll59 ; We used to produce spills+reloads for a Q register with zero cycle zeroing
/external/mesa3d/docs/relnotes/
D20.0.8.rst82 - meson: Disable GCC's dead store elimination for memory zeroing custom
143 - intel/fs: Fix unused texture coordinate zeroing on Gen4-5
D20.1.1.rst120 - intel/fs: Fix unused texture coordinate zeroing on Gen4-5
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64.td112 // implemented this should tell the compiler to use the zeroing pseudos to
123 : SubtargetFeature<"use-experimental-zeroing-pseudos",
148 … "Has zero-cycle zeroing instructions for generic registers">;
151 "Has zero-cycle zeroing instructions for FP registers">;
154 "Has zero-cycle zeroing instructions",
161 "The zero-cycle floating-point zeroing instruction has a bug">;
/external/rust/crates/nix/
DCONVENTIONS.md80 allows us to avoid the overhead incurred by zeroing or otherwise initializing
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve2-intrinsics-uniform-dsp-zeroing.ll1 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -asm-verbose=0 -mattr=+use-experimental-zeroing-…
Darm64-zero-cycle-zeroing.ll76 ; We used to produce spills+reloads for a Q register with zero cycle zeroing
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64.td125 … "Has zero-cycle zeroing instructions for generic registers">;
128 "Has zero-cycle zeroing instructions for FP registers">;
131 "Has zero-cycle zeroing instructions",
138 "The zero-cycle floating-point zeroing instruction has a bug">;
/external/rust/crates/futures-io/src/
Dlib.rs70 Initializer::zeroing() in initializer()
/external/llvm/lib/Target/WebAssembly/
DREADME.txt91 WebAssembly registers are implicitly initialized to zero. Explicit zeroing is
/external/rust/crates/futures-util/src/compat/
Dcompat01as03.rs444 Initializer::zeroing() in initializer()
/external/llvm/lib/Target/AArch64/
DAArch64.td53 "Has zero-cycle zeroing instructions">;
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrVecCompiler.td176 // zeroing.
250 // If the bits are not zero we have to fall back to explicitly zeroing by
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td176 // zeroing.
250 // If the bits are not zero we have to fall back to explicitly zeroing by
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DREADME.txt128 WebAssembly registers are implicitly initialized to zero. Explicit zeroing is
/external/llvm-project/llvm/lib/Target/WebAssembly/
DREADME.txt128 WebAssembly registers are implicitly initialized to zero. Explicit zeroing is

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