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/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc442 int zn_inputs[] = {-5, -20, 9, 8}; in MlaMlsHelper() local
453 InsrHelper(&masm, zn, zn_inputs); in MlaMlsHelper()
510 ASSERT_EQUAL_SVE(zn_inputs, z2.WithLaneSize(lane_size_in_bits)); in MlaMlsHelper()
519 int mla_dn_expected[] = {mla[0], zn_inputs[1], mla[2], mla[3]}; in MlaMlsHelper()
531 int mls_dn_expected[] = {mls[0], zn_inputs[1], mls[2], mls[3]}; in MlaMlsHelper()
4543 const Tn& zn_inputs, in IntBinArithHelper() argument
4551 InsrHelper(&masm, src_a, zn_inputs); in IntBinArithHelper()
4592 ASSERT_EQUAL_SVE_LANE(zn_inputs[i], zd_1, lane); in IntBinArithHelper()
5104 const T& zn_inputs, in IntArithHelper() argument
5112 InsrHelper(&masm, zn, zn_inputs); in IntArithHelper()
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