Searched refs:zreg (Results 1 – 5 of 5) sorted by relevance
| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | select-select.mir | 104 ; G_SELECT cc, 0, 1 -> CSINC zreg, zreg, cc
132 ; G_SELECT cc 0, -1 -> CSINV zreg, zreg cc
160 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
189 ; G_SELECT cc, -1, f -> CSINV f, zreg, inv_cc
218 ; G_SELECT cc, t, 1 -> CSINC t, zreg, cc
247 ; G_SELECT cc, t, -1 -> CSINC t, zreg, cc
276 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
303 ; G_SELECT cc, t, 1 -> CSINC t, zreg, cc
330 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
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| /external/llvm-project/lldb/source/Plugins/Process/Utility/ |
| D | RegisterInfos_arm64_sve.h | 311 #define DEFINE_VREG_SVE(vreg, zreg) \ argument
314 VREG_KIND(vreg), g_contained_##zreg, g_sve_##vreg##_invalidates, \
319 #define DEFINE_FPU_PSEUDO_SVE(reg, size, zreg) \ argument
322 LLDB_KIND(fpu_##reg), g_contained_##zreg, g_sve_##reg##_invalidates, \
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | Hexagon.td | 27 def ExtensionZReg: SubtargetFeature<"zreg", "UseZRegOps", "true",
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | Hexagon.td | 30 def ExtensionZReg: SubtargetFeature<"zreg", "UseZRegOps", "true",
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4003 unsigned zreg = in MatchAndEmitInstruction() local
4008 Operands[2] = AArch64Operand::CreateReg(zreg, false, Op.getStartLoc(), in MatchAndEmitInstruction()
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