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Searched refs:zsa (Results 1 – 25 of 63) sorted by relevance

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/external/mesa3d/src/gallium/drivers/freedreno/
Dfreedreno_state.h35 return ctx->zsa && ctx->zsa->depth.enabled; in fd_depth_enabled()
40 return ctx->zsa && ctx->zsa->depth.writemask; in fd_depth_write_enabled()
45 return ctx->zsa && ctx->zsa->stencil[0].enabled; in fd_stencil_enabled()
/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_state.h37 return ctx->zsa && ctx->zsa->depth.enabled; in etna_depth_enabled()
43 return ctx->zsa && ctx->zsa->stencil[0].enabled; in etna_stencil_enabled()
Detnaviv_state.c494 ctx->zsa = zs; in etna_zsa_state_bind()
683 struct pipe_depth_stencil_alpha_state *zsa_state = ctx->zsa; in etna_update_zsa()
684 struct etna_zsa_state *zsa = etna_zsa_state(zsa_state); in etna_update_zsa() local
690 if (zsa->z_write_enabled) { in etna_update_zsa()
693 !zsa->stencil_enabled && in etna_update_zsa()
702 if (zsa->z_test_enabled) { in etna_update_zsa()
704 !zsa->stencil_modified && in etna_update_zsa()
711 new_pe_depth = VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(zsa->z_test_enabled ? in etna_update_zsa()
714 COND(zsa->z_write_enabled, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) | in etna_update_zsa()
716 COND(!late_z_write && !late_z_test && !zsa->stencil_enabled, in etna_update_zsa()
[all …]
Detnaviv_zsa.h51 etna_zsa_state(struct pipe_depth_stencil_alpha_state *zsa) in etna_zsa_state() argument
53 return (struct etna_zsa_state *)zsa; in etna_zsa_state()
Detnaviv_emit.c417 /*00E08*/ EMIT_STATE(RA_EARLY_DEPTH, etna_zsa_state(ctx->zsa)->RA_DEPTH_CONFIG); in etna_emit_state()
433 /*01400*/ EMIT_STATE(PE_DEPTH_CONFIG, (etna_zsa_state(ctx->zsa)->PE_DEPTH_CONFIG | in etna_emit_state()
451 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_OP[ccw]; in etna_emit_state()
455 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG[ccw]; in etna_emit_state()
459 uint32_t val = etna_zsa_state(ctx->zsa)->PE_ALPHA_OP; in etna_emit_state()
496 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT; in etna_emit_state()
515 …/*014B8*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT2, etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT2[ccw]… in etna_emit_state()
/external/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_zsa.h59 fd6_zsa_stateobj(struct pipe_depth_stencil_alpha_state *zsa) in fd6_zsa_stateobj() argument
61 return (struct fd6_zsa_stateobj *)zsa; in fd6_zsa_stateobj()
72 return fd6_zsa_stateobj(ctx->zsa)->stateobj[variant]; in fd6_zsa_state()
Dfd6_emit.c584 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa); in compute_ztest_mode() local
590 if (fs->no_earlyz || fs->writes_pos || !zsa->base.depth.enabled) { in compute_ztest_mode()
592 } else if ((fs->has_kill || zsa->alpha_test) && in compute_ztest_mode()
593 (zsa->base.depth.writemask || !pfb->zsbuf)) { in compute_ztest_mode()
628 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa); in compute_lrz_state() local
631 lrz = zsa->lrz; in compute_lrz_state()
645 if (zsa->base.depth.enabled && in compute_lrz_state()
651 if (zsa->invalidate_lrz || !rsc->lrz_valid) { in compute_lrz_state()
676 if (zsa->base.depth.writemask) { in compute_lrz_state()
/external/mesa3d/src/gallium/drivers/freedreno/a2xx/
Dfd2_zsa.h46 fd2_zsa_stateobj(struct pipe_depth_stencil_alpha_state *zsa) in fd2_zsa_stateobj() argument
48 return (struct fd2_zsa_stateobj *)zsa; in fd2_zsa_stateobj()
Dfd2_emit.c238 struct fd2_zsa_stateobj *zsa = fd2_zsa_stateobj(ctx->zsa); in fd2_emit_state() local
257 uint32_t val = zsa->rb_depthcontrol; in fd2_emit_state()
268 OUT_RING(ring, zsa->rb_stencilrefmask_bf | in fd2_emit_state()
270 OUT_RING(ring, zsa->rb_stencilrefmask | in fd2_emit_state()
272 OUT_RING(ring, zsa->rb_alpha_ref); in fd2_emit_state()
369 OUT_RING(ring, zsa->rb_colorcontrol | blend->rb_colorcontrol); in fd2_emit_state()
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/
Dfd3_zsa.h47 fd3_zsa_stateobj(struct pipe_depth_stencil_alpha_state *zsa) in fd3_zsa_stateobj() argument
49 return (struct fd3_zsa_stateobj *)zsa; in fd3_zsa_stateobj()
Dfd3_emit.c529 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control | in fd3_emit_state()
549 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa); in fd3_emit_state() local
553 OUT_RING(ring, zsa->rb_alpha_ref); in fd3_emit_state()
556 OUT_RING(ring, zsa->rb_stencil_control); in fd3_emit_state()
559 OUT_RING(ring, zsa->rb_stencilrefmask | in fd3_emit_state()
561 OUT_RING(ring, zsa->rb_stencilrefmask_bf | in fd3_emit_state()
566 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control; in fd3_emit_state()
/external/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_zsa.h49 fd5_zsa_stateobj(struct pipe_depth_stencil_alpha_state *zsa) in fd5_zsa_stateobj() argument
51 return (struct fd5_zsa_stateobj *)zsa; in fd5_zsa_stateobj()
Dfd5_emit.c551 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa); in fd5_emit_state() local
552 uint32_t rb_alpha_control = zsa->rb_alpha_control; in fd5_emit_state()
561 OUT_RING(ring, zsa->rb_stencil_control); in fd5_emit_state()
566 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa); in fd5_emit_state() local
570 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl; in fd5_emit_state()
574 else if (emit->binning_pass && blend->lrz_write && zsa->lrz_write) in fd5_emit_state()
583 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa); in fd5_emit_state() local
587 OUT_RING(ring, zsa->rb_stencilrefmask | in fd5_emit_state()
589 OUT_RING(ring, zsa->rb_stencilrefmask_bf | in fd5_emit_state()
594 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa); in fd5_emit_state() local
[all …]
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/
Dfd4_zsa.h48 fd4_zsa_stateobj(struct pipe_depth_stencil_alpha_state *zsa) in fd4_zsa_stateobj() argument
50 return (struct fd4_zsa_stateobj *)zsa; in fd4_zsa_stateobj()
Dfd4_emit.c545 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa); in fd4_emit_state() local
547 uint32_t rb_alpha_control = zsa->rb_alpha_control; in fd4_emit_state()
556 OUT_RING(ring, zsa->rb_stencil_control); in fd4_emit_state()
557 OUT_RING(ring, zsa->rb_stencil_control2); in fd4_emit_state()
561 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa); in fd4_emit_state() local
565 OUT_RING(ring, zsa->rb_stencilrefmask | in fd4_emit_state()
567 OUT_RING(ring, zsa->rb_stencilrefmask_bf | in fd4_emit_state()
572 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa); in fd4_emit_state() local
577 OUT_RING(ring, zsa->rb_depth_control | in fd4_emit_state()
587 OUT_RING(ring, zsa->gras_alpha_control | in fd4_emit_state()
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_emit.c107 vc4->zsa->config_bits[0]) & rasosm_mask_out); in vc4_emit_state()
110 vc4->zsa->config_bits[1]); in vc4_emit_state()
113 vc4->zsa->config_bits[2]) & ez_enable_mask_out); in vc4_emit_state()
Dvc4_draw.c480 if (vc4->zsa && vc4->framebuffer.zsbuf) { in vc4_draw_vbo()
484 if (vc4->zsa->base.depth.enabled) { in vc4_draw_vbo()
489 if (vc4->zsa->base.stencil[0].enabled) { in vc4_draw_vbo()
/external/llvm-project/clang/test/CodeGenCXX/
Dtrivial-auto-var-init.cpp247 int zsa[0]; in test_zsa() local
248 used(zsa); in test_zsa()
/external/mesa3d/src/gallium/drivers/v3d/
Dv3dx_emit.c517 if (v3d->zsa->base.depth.enabled) { in v3dX()
519 v3d->zsa->base.depth.writemask; in v3dX()
523 v3d->zsa->base.depth.func; in v3dX()
529 v3d->zsa->base.stencil[0].enabled; in v3dX()
646 struct pipe_stencil_state *front = &v3d->zsa->base.stencil[0]; in v3dX()
647 struct pipe_stencil_state *back = &v3d->zsa->base.stencil[1]; in v3dX()
651 v3d->zsa->stencil_front, config) { in v3dX()
659 v3d->zsa->stencil_back, config) { in v3dX()
Dv3dx_draw.c994 switch (v3d->zsa->ez_state) { in v3d_update_job_ez()
1008 job->ez_state = v3d->zsa->ez_state; in v3d_update_job_ez()
1009 else if (job->ez_state != v3d->zsa->ez_state) in v3d_update_job_ez()
1389 if (v3d->zsa && job->zsbuf && v3d->zsa->base.depth.enabled) { in v3d_draw_vbo()
1394 if (v3d->zsa->base.depth.writemask) in v3d_draw_vbo()
1399 if (v3d->zsa && job->zsbuf && v3d->zsa->base.stencil[0].enabled) { in v3d_draw_vbo()
1407 if (v3d->zsa->base.stencil[0].writemask || in v3d_draw_vbo()
1408 v3d->zsa->base.stencil[1].writemask) { in v3d_draw_vbo()
/external/mesa3d/src/gallium/drivers/panfrost/
Dpan_cmdstream.c410 const struct panfrost_zsa_state *zsa = ctx->depth_stencil; in panfrost_prepare_midgard_fs_state() local
426 (zsa->base.depth.enabled && zsa->base.depth.func != PIPE_FUNC_ALWAYS) || in panfrost_prepare_midgard_fs_state()
427 zsa->base.stencil[0].enabled; in panfrost_prepare_midgard_fs_state()
490 const struct panfrost_zsa_state *zsa = ctx->depth_stencil; in panfrost_prepare_fs_state() local
505 state->multisample_misc.depth_function = zsa->base.depth.enabled ? in panfrost_prepare_fs_state()
506 panfrost_translate_compare_func(zsa->base.depth.func) : in panfrost_prepare_fs_state()
509 state->multisample_misc.depth_write_mask = zsa->base.depth.writemask; in panfrost_prepare_fs_state()
514 state->stencil_mask_misc.stencil_mask_front = zsa->stencil_mask_front; in panfrost_prepare_fs_state()
515 state->stencil_mask_misc.stencil_mask_back = zsa->stencil_mask_back; in panfrost_prepare_fs_state()
516 state->stencil_mask_misc.stencil_enable = zsa->base.stencil[0].enabled; in panfrost_prepare_fs_state()
[all …]
Dpan_context.c1187 const struct pipe_depth_stencil_alpha_state *zsa) in panfrost_create_depth_stencil_state() argument
1190 so->base = *zsa; in panfrost_create_depth_stencil_state()
1192 pan_pipe_to_stencil(&zsa->stencil[0], &so->stencil_front); in panfrost_create_depth_stencil_state()
1193 so->stencil_mask_front = zsa->stencil[0].writemask; in panfrost_create_depth_stencil_state()
1195 if (zsa->stencil[1].enabled) { in panfrost_create_depth_stencil_state()
1196 pan_pipe_to_stencil(&zsa->stencil[1], &so->stencil_back); in panfrost_create_depth_stencil_state()
1197 so->stencil_mask_back = zsa->stencil[1].writemask; in panfrost_create_depth_stencil_state()
1204 assert(!zsa->alpha.enabled); in panfrost_create_depth_stencil_state()
1207 assert(!zsa->depth.bounds_test); in panfrost_create_depth_stencil_state()
/external/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv50_state_validate.c342 if (nv50->zsa && nv50->zsa->pipe.alpha.enabled && in nv50_validate_derived_2()
398 PUSH_SPACE(push, nv50->zsa->size); in nv50_validate_zsa()
399 PUSH_DATAp(push, nv50->zsa->state, nv50->zsa->size); in nv50_validate_zsa()
483 if (!ctx_to->zsa) in nv50_switch_pipe_context()
/external/mesa3d/src/gallium/drivers/nouveau/nvc0/
Dnvc0_state_validate.c561 PUSH_SPACE(push, nvc0->zsa->size); in nvc0_validate_zsa()
562 PUSH_DATAp(push, nvc0->zsa->state, nvc0->zsa->size); in nvc0_validate_zsa()
735 bool zs = nvc0->zsa && in nvc0_validate_fp_zsa_rast()
736 (nvc0->zsa->pipe.depth.enabled || nvc0->zsa->pipe.stencil[0].enabled); in nvc0_validate_fp_zsa_rast()
756 if (nvc0->zsa && nvc0->zsa->pipe.alpha.enabled && in nvc0_validate_zsa_fb()
907 if (!ctx_to->zsa) in nvc0_switch_pipe_context()
/external/mesa3d/src/gallium/drivers/nouveau/nv30/
Dnv30_state_validate.c309 PUSH_SPACE(push, nv30->zsa->size); in nv30_validate_zsa()
310 PUSH_DATAp(push, nv30->zsa->data, nv30->zsa->size); in nv30_validate_zsa()
456 if (!nv30->zsa) in nv30_state_context_switch()

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