| /external/grpc-grpc/test/cpp/util/ |
| D | metrics_server.cc | 40 void QpsGauge::Incr() { in Incr() function in grpc::testing::QpsGauge
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCOptAddrMode.cpp | 221 int64_t Incr; in tryToCombine() local
343 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses()
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| /external/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCOptAddrMode.cpp | 221 int64_t Incr; in tryToCombine() local
343 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses()
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| /external/tensorflow/tensorflow/core/lib/gtl/ |
| D | cleanup_test.cc | 267 void Incr(volatile int* ip) { ++*ip; } in Incr() function
268 void Incr() { Incr(&i); } in Incr() function
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 412 Register Incr = I->getOperand(2).getReg(); in expandAtomicBinOpSubword() local
634 Register Incr = I->getOperand(2).getReg(); in expandAtomicBinOp() local
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| D | MipsISelLowering.cpp | 1549 Register Incr = MI.getOperand(2).getReg(); in emitAtomicBinary() local
1660 Register Incr = MI.getOperand(2).getReg(); in emitAtomicBinaryPartword() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 412 Register Incr = I->getOperand(2).getReg(); in expandAtomicBinOpSubword() local
634 Register Incr = I->getOperand(2).getReg(); in expandAtomicBinOp() local
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| D | MipsISelLowering.cpp | 1551 Register Incr = MI.getOperand(2).getReg(); in emitAtomicBinary() local
1662 Register Incr = MI.getOperand(2).getReg(); in emitAtomicBinaryPartword() local
|
| /external/swiftshader/third_party/subzero/crosstest/ |
| D | test_vector_ops_main.cpp | 34 Ty Incr; in getTestVectors() local
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 538 int Incr; in updateOffset() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 530 int Incr; in updateOffset() local
|
| /external/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | IndVarSimplify.cpp | 225 auto *Incr = dyn_cast<BinaryOperator>(PN->getIncomingValue(BackEdge)); in handleFloatingPointIV() local
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfUnit.cpp | 575 int Incr = (LittleEndian ? 1 : -1); in addConstantFPValue() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfUnit.cpp | 521 int Incr = (LittleEndian ? 1 : -1); in addConstantFPValue() local
|
| /external/llvm-project/llvm/lib/Frontend/OpenMP/ |
| D | OMPIRBuilder.cpp | 956 Value *Incr = Step; in createCanonicalLoop() local
|
| /external/llvm/lib/Transforms/Scalar/ |
| D | IndVarSimplify.cpp | 259 auto *Incr = dyn_cast<BinaryOperator>(PN->getIncomingValue(BackEdge)); in handleFloatingPointIV() local
|
| D | LoopStrengthReduce.cpp | 1851 BinaryOperator *Incr = in OptimizeShadowIV() local
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1144 unsigned Incr = MI.getOperand(2).getReg(); in emitAtomicBinary() local
1243 unsigned Incr = MI.getOperand(2).getReg(); in emitAtomicBinaryPartword() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 1881 int SubReg = 0, End = NumRegs, Incr = 1; in copyPhysRegTuple() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | IndVarSimplify.cpp | 321 auto *Incr = dyn_cast<BinaryOperator>(PN->getIncomingValue(BackEdge)); in handleFloatingPointIV() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 2813 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic()
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 3524 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 2461 int SubReg = 0, End = NumRegs, Incr = 1; in copyPhysRegTuple() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 1732 Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 2726 int SubReg = 0, End = NumRegs, Incr = 1; in copyPhysRegTuple() local
|