| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypesGeneric.cpp | 506 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_SELECT() local
544 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
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| D | LegalizeIntegerTypes.cpp | 2910 SDValue LL, LH, RL, RH; in ExpandIntRes_Logical() local
2923 SDValue LL, LH, RL, RH; in ExpandIntRes_MUL() local
3070 SDValue LL, LH, RL, RH; in ExpandIntRes_MULFIX() local
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| D | LegalizeVectorTypes.cpp | 1677 SDValue LL, LH, RL, RH; in SplitVecRes_SETCC() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypesGeneric.cpp | 525 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_SELECT() local
547 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
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| D | LegalizeIntegerTypes.cpp | 2164 SDValue LL, LH, RL, RH; in ExpandIntRes_Logical() local
2177 SDValue LL, LH, RL, RH; in ExpandIntRes_MUL() local
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| D | LegalizeVectorTypes.cpp | 1224 SDValue LL, LH, RL, RH; in SplitVecRes_SETCC() local
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| D | DAGCombiner.cpp | 5261 SDValue Lo, Hi, LL, LH, RL, RH; in SplitVSETCC() local
5676 SDValue Lo, Hi, CCLo, CCHi, LL, LH, RL, RH; in visitVSELECT() local
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypesGeneric.cpp | 510 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_SELECT() local
548 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
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| D | LegalizeIntegerTypes.cpp | 3236 SDValue LL, LH, RL, RH; in ExpandIntRes_Logical() local
3249 SDValue LL, LH, RL, RH; in ExpandIntRes_MUL() local
3402 SDValue LL, LH, RL, RH; in ExpandIntRes_MULFIX() local
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| D | LegalizeVectorTypes.cpp | 1814 SDValue LL, LH, RL, RH; in SplitVecRes_SETCC() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | LowerMatrixIntrinsics.cpp | 743 Value *RH = Builder.CreateExtractElement(Rhs.getColumn(J), K); in LowerMultiply() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1614 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2); in propagateRegCopy() local
1701 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1709 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2); in propagateRegCopy() local
1807 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf()
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| D | HexagonConstPropagation.cpp | 2522 bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, in evaluateHexRSEQ32()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1699 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2); in propagateRegCopy() local
1797 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf()
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| D | HexagonConstPropagation.cpp | 2517 bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, in evaluateHexRSEQ32()
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| /external/llvm-project/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 675 SDValue LH, RH; in TryExpandADDWithMul() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 676 SDValue LH, RH; in TryExpandADDWithMul() local
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 701 SDValue LH, RH; in TryExpandADDWithMul() local
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| /external/deqp/framework/common/ |
| D | tcuCompressedTexture.cpp | 775 const deUint8 RH = extend6To8((deUint8)((RH1 << 1) | RH2)); in decompressETC2Block() local
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| /external/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | LowerMatrixIntrinsics.cpp | 1049 Value *RH = Builder.CreateExtractElement(B.getColumn(J), K); in emitMatrixMultiply() local
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 2953 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63); in lowerSMUL_LOHI() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 3470 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63); in lowerSMUL_LOHI() local
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| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 3522 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63); in lowerSMUL_LOHI() local
|