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/external/llvm-project/llvm/test/Transforms/Attributor/
Dchain.ll13 ; CHECK_1-NEXT: [[BC1:%.*]] = bitcast i32* [[ARG]] to i8*
14 ; CHECK_1-NEXT: call void @foo(i8* dereferenceable_or_null(8) [[BC1]])
21 ; CHECK_5-NEXT: [[BC1:%.*]] = bitcast i32* [[ARG]] to i8*
22 ; CHECK_5-NEXT: call void @foo(i8* nonnull dereferenceable(8) [[BC1]])
Dreturned.ll951 ; IS__TUNIT____-NEXT: [[BC1:%.*]] = bitcast i32* [[B]] to double*
954 ; IS__TUNIT____-NEXT: [[PHI:%.*]] = phi double* [ [[BC1]], [[IF_THEN]] ], [ [[BC0]], [[ENTRY:%.*…
970 ; IS__CGSCC____-NEXT: [[BC1:%.*]] = bitcast i32* [[B]] to double*
973 ; IS__CGSCC____-NEXT: [[PHI:%.*]] = phi double* [ [[BC1]], [[IF_THEN]] ], [ [[BC0]], [[ENTRY:%.*…
1020 ; IS__TUNIT____-NEXT: [[BC1:%.*]] = bitcast i32* [[B]] to double*
1021 ; IS__TUNIT____-NEXT: ret double* [[BC1]]
1037 ; IS__CGSCC____-NEXT: [[BC1:%.*]] = bitcast i32* [[B]] to double*
1038 ; IS__CGSCC____-NEXT: ret double* [[BC1]]
1091 ; IS__TUNIT____-NEXT: [[BC1:%.*]] = bitcast i32* [[B]] to double*
1092 ; IS__TUNIT____-NEXT: ret double* [[BC1]]
[all …]
Dreadattrs.ll411 ; CHECK-NEXT: [[BC1:%.*]] = bitcast i32* [[BC0]] to i8*
412 ; CHECK-NEXT: [[BC2:%.*]] = bitcast i8* [[BC1]] to i32*
/external/llvm/test/tools/gold/X86/
Dparallel.ll4 ; RUN: llvm-dis %t.opt.bc1 -o - | FileCheck --check-prefix=CHECK-BC1 %s
20 ; CHECK-BC1: declare void @foo
21 ; CHECK-BC1: define void @bar
/external/llvm-project/llvm/test/Transforms/PhaseOrdering/X86/
Dshuffle.ll167 ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <8 x i32> <i32 4,…
168 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> undef, <8 x i32> <i3…
183 ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <8 x i32> <i32 4,…
184 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> undef, <8 x i32> <i3…
199 ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> undef, <16 x i32> <i32 8…
200 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <16 x i8> [[BC1]], <16 x i8> undef, <16 x i32> <i…
215 ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> undef, <16 x i32> <i32 8…
216 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <16 x i8> [[BC1]], <16 x i8> undef, <16 x i32> <i…
231 ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 2,…
232 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> undef, <4 x i32> <i3…
[all …]
/external/llvm-project/llvm/test/tools/gold/X86/
Dparallel.ll5 ; RUN: llvm-dis %t.1.5.precodegen.bc -o - | FileCheck --check-prefix=CHECK-BC1 %s
22 ; CHECK-BC1: declare dso_local void @foo
23 ; CHECK-BC1: define dso_local void @bar
/external/llvm-project/llvm/test/tools/gold/X86/v1.12/
Dthinlto_emit_linked_objects.ll36 ; RUN: llvm-bcanalyzer --dump %t1.o.thinlto.bc | FileCheck %s -check-prefixes=CHECK-BC1
37 ; CHECK-BC1: <GLOBALVAL_SUMMARY_BLOCK
38 ; CHECK-BC1: <FLAGS op0=33/>
39 ; CHECK-BC1: </GLOBALVAL_SUMMARY_BLOCK
/external/llvm-project/llvm/test/Transforms/VectorCombine/X86/
Dshuffle.ll96 ; SSE-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[PERMIL]] to <16 x i8>
97 ; SSE-NEXT: [[ADD:%.*]] = shl <16 x i8> [[BC1]], <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1…
106 ; AVX-NEXT: [[BC1:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> undef, <16 x i32> <i32 12,…
107 ; AVX-NEXT: [[ADD:%.*]] = shl <16 x i8> [[BC1]], <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1…
127 ; SSE-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[PERMIL]] to <8 x i16>
128 ; SSE-NEXT: [[ADD:%.*]] = shl <8 x i16> [[BC1]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 …
137 ; AVX-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <8 x i32> <i32 6, i…
138 ; AVX-NEXT: [[ADD:%.*]] = shl <8 x i16> [[BC1]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 …
/external/llvm-project/llvm/test/Transforms/InstSimplify/
Dcast.ll15 %BC1 = bitcast i8* %V to i32*
16 %BC2 = bitcast i32* %BC1 to i8*
/external/mesa3d/src/gallium/drivers/v3d/
Dv3dx_format_table.c179 FORMAT(DXT1_RGB, NO, BC1, SWIZ_XYZ1, 16, 0),
180 FORMAT(DXT1_SRGB, NO, BC1, SWIZ_XYZ1, 16, 0),
181 FORMAT(DXT1_RGBA, NO, BC1, SWIZ_XYZW, 16, 0),
182 FORMAT(DXT1_SRGBA, NO, BC1, SWIZ_XYZW, 16, 0),
/external/llvm-project/llvm/test/Transforms/ConstantHoisting/AArch64/
Dconst-hoist-gep.ll10 ; CHECK-NEXT: %[[BC1:[a-z0-9_]+]] = bitcast i32* %const to i8*
11 ; CHECK-NEXT: %[[M1:[a-z0-9_]+]] = getelementptr i8, i8* %[[BC1]], i32 4
/external/llvm-project/llvm/test/Transforms/ConstantHoisting/ARM/
Dconst-hoist-gep.ll12 ; CHECK-NEXT: %[[BC1:[a-z0-9_]+]] = bitcast i32* %[[C2]] to i8*
13 ; CHECK-NEXT: %[[M1:[a-z0-9_]+]] = getelementptr i8, i8* %[[BC1]], i32 4
/external/llvm-project/clang/test/Driver/
Dhip-binding.hip18 // RDCS: # "amdgcn-amd-amdhsa" - "clang", inputs: ["[[IN:.*hip-binding.hip]]"], output: "[[BC1:.*bc…
21 // RDCS: # "x86_64-unknown-linux-gnu" - "offload bundler", inputs: ["[[BC1]]", "[[BC2]]", "[[HOSTOB…
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dload-bitcast-select.ll59 ; CHECK-NEXT: [[BC1:%.*]] = bitcast float* [[SEL]] to i32*
60 ; CHECK-NEXT: [[LD:%.*]] = load i32, i32* [[BC1]], align 4
Dbitcast.ll139 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x float> [[A:%.*]] to <2 x i64>
141 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i64> [[BC2]], [[BC1]]
156 ; CHECK-NEXT: [[BC1:%.*]] = bitcast i128 [[A:%.*]] to <2 x i64>
157 ; CHECK-NEXT: [[OR:%.*]] = or <2 x i64> [[BC1]], [[B:%.*]]
171 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[A:%.*]] to i128
172 ; CHECK-NEXT: [[XOR:%.*]] = xor i128 [[BC1]], [[B:%.*]]
365 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <2 x i32> [[A:%.*]] to <1 x i64>
366 ; CHECK-NEXT: [[EXT:%.*]] = extractelement <1 x i64> [[BC1]], i32 0
Dlogical-select.ll345 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[SEXT]] to <2 x i64>
346 ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i64> [[BC1]], [[A:%.*]]
570 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
571 ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i64> [[SIA]], [[BC1]]
Dtrunc.ll557 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <2 x i64> [[V:%.*]] to <4 x i32>
558 ; CHECK-NEXT: [[EXT:%.*]] = extractelement <4 x i32> [[BC1]], i32 2
/external/harfbuzz_ng/test/shaping/data/in-house/tests/
Dmacos.tests6 …--font-funcs ot:U+0BA4,U+0BCA,U+0B95,U+0BC1,U+0B95,U+0BCD,U+0B95,U+0BAA,U+0BCD,U+0BAA,U+0B9F,U+0BC…
25 …--font-funcs ot:U+0BA4,U+0BCA,U+0B95,U+0BC1,U+0B95,U+0BCD,U+0B95,U+0BAA,U+0BCD,U+0BAA,U+0B9F,U+0BC…
44 …--font-funcs ot:U+0BA4,U+0BCA,U+0B95,U+0BC1,U+0B95,U+0BCD,U+0B95,U+0BAA,U+0BCD,U+0BAA,U+0B9F,U+0BC…
/external/llvm-project/llvm/test/Transforms/WholeProgramDevirt/
Dimport.ll40 ; VCP: [[BC1:%.*]] = bitcast i8* [[GEP1]] to i32*
41 ; VCP: [[LOAD1:%.*]] = load i32, i32* [[BC1]]
/external/mesa3d/docs/relnotes/
D17.0.7.rst97 - anv/formats: Update the three-channel BC1 mappings
D17.1.1.rst113 - anv/formats: Update the three-channel BC1 mappings
/external/llvm/test/Transforms/InstCombine/
Dlogical-select.ll268 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[SEXT]] to <2 x i64>
269 ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i64> [[BC1]], %a
/external/llvm/lib/IR/
DAutoUpgrade.cpp1309 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); in UpgradeIntrinsicCall() local
1311 CallInst *NewCall = Builder.CreateCall(NewFn, {BC0, BC1}, Name); in UpgradeIntrinsicCall()
/external/skia/
DRELEASE_NOTES.txt641 * Added support for BC1 RGBA compressed textures
657 * Added BC1 compressed format support. Metal and Vulkan seem to only support the BC
/external/skia/site/docs/user/release/
Drelease_notes.md581 * Added support for BC1 RGBA compressed textures
597 * Added BC1 compressed format support. Metal and Vulkan seem to only support the BC

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