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Searched refs:BRW_ALIGN_1 (Results 1 – 20 of 20) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_vec4_generator.cpp68 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_math_gen6()
227 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_tex()
305 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_tex()
391 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_urb_write_allocate()
438 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_set_write_offset()
478 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_set_vertex_count()
536 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_svb_set_destination_index()
548 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_set_dword_2()
566 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_prepare_channel_masks()
630 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_set_channel_masks()
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Dbrw_eu_emit.c146 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_dest()
169 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_dest()
283 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src0()
291 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src0()
298 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src0()
399 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src1()
405 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src1()
808 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_alu3()
1112 brw_get_default_access_mode(p) == BRW_ALIGN_1 && in ALU1()
1253 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_F32TO16()
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Dbrw_clip_util.c96 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_clip_project_position()
211 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_clip_interp_vertex()
232 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_clip_interp_vertex()
Dbrw_disasm.c780 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in dest()
831 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; in dest_3src()
1110 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; in src0_3src()
1196 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; in src1_3src()
1269 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; in src2_3src()
1491 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in src0()
1553 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in src1()
1696 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_disassemble_inst()
Dbrw_eu_validate.c314 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in invalid_values()
847 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in general_restrictions_based_on_operand_types()
893 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 && in general_restrictions_based_on_operand_types()
1693 unsigned dst_subreg = brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 ? in vector_immediate_restrictions()
1815 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 && in special_requirements_for_handling_double_precision_data_types()
Dtest_eu_compact.cpp308 brw_set_default_access_mode(p, BRW_ALIGN_1); in run_tests()
Dbrw_eu_defines.h97 #define BRW_ALIGN_1 0 macro
Dbrw_clip_unfilled.c86 brw_set_default_access_mode(p, BRW_ALIGN_1); in compute_tri_direction()
Dbrw_inst.h319 FK(access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
374 FK(3src_access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
Dbrw_compile_sf.c663 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_emit_point_sprite_setup()
Dtest_eu_validate.cpp494 brw_set_default_access_mode(p, BRW_ALIGN_1); in TEST_P()
566 { BRW_ALIGN_1, devinfo.gen >= 10 },
Dbrw_fs_generator.cpp1985 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_code()
/external/igt-gpu-tools/assembler/
Dgen8_instruction.c53 if (gen8_access_mode(inst) == BRW_ALIGN_1) { in gen8_set_dst()
69 assert (gen8_access_mode(inst) == BRW_ALIGN_1); in gen8_set_dst()
188 if (gen8_access_mode(inst) == BRW_ALIGN_1) { in gen8_set_src0()
229 assert (gen8_access_mode(inst) == BRW_ALIGN_1); in gen8_set_src0()
277 if (gen8_access_mode(inst) == BRW_ALIGN_1) { in gen8_set_src1()
317 assert (gen8_access_mode(inst) == BRW_ALIGN_1); in gen8_set_src1()
Dgen8_disasm.c388 if (gen8_access_mode(inst) == BRW_ALIGN_1) in dest()
729 if (gen8_access_mode(inst) == BRW_ALIGN_1) in src0()
767 if (gen8_access_mode(inst) == BRW_ALIGN_1) in src1()
845 if (gen8_access_mode(insn) == BRW_ALIGN_1) { in gen8_disassemble()
Dbrw_eu_emit.c121 if (insn->header.access_mode == BRW_ALIGN_1) { in brw_set_dest()
139 if (insn->header.access_mode == BRW_ALIGN_1) { in brw_set_dest()
294 if (insn->header.access_mode == BRW_ALIGN_1) { in brw_set_src0()
306 if (insn->header.access_mode == BRW_ALIGN_1) { in brw_set_src0()
314 if (insn->header.access_mode == BRW_ALIGN_1) { in brw_set_src0()
385 if (insn->header.access_mode == BRW_ALIGN_1) { in brw_set_src1()
397 if (insn->header.access_mode == BRW_ALIGN_1) in brw_set_src1()
403 if (insn->header.access_mode == BRW_ALIGN_1) { in brw_set_src1()
2342 brw_set_access_mode(p, BRW_ALIGN_1); in brw_urb_WRITE()
2601 brw_set_access_mode(p, BRW_ALIGN_1); in brw_shader_time_add()
Dbrw_disasm.c517 if (inst->header.access_mode == BRW_ALIGN_1) in dest()
890 else if (inst->header.access_mode == BRW_ALIGN_1) in src0()
950 else if (inst->header.access_mode == BRW_ALIGN_1) in src1()
1054 if (inst->header.access_mode == BRW_ALIGN_1) in brw_disasm()
Dbrw_defines.h548 #define BRW_ALIGN_1 0 macro
Dgram.y289 access_mode(insn) == BRW_ALIGN_1 && in validate_dst_reg()
319 if (access_mode(insn) == BRW_ALIGN_1 && in validate_src_reg()
583 options->access_mode = BRW_ALIGN_1; in add_option()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_ff_gs_emit.c451 brw_set_default_access_mode(p, BRW_ALIGN_1); in gen6_sol_program()
/external/mesa3d/src/intel/tools/
Di965_gram.y536 options->access_mode = BRW_ALIGN_1; in add_instruction_option()