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Searched refs:BRW_CHANNEL_Z (Results 1 – 12 of 12) sorted by relevance

/external/igt-gpu-tools/assembler/
Dgen8_disasm.c514 swz_z == BRW_CHANNEL_Z && in src_da16()
565 swz_z == BRW_CHANNEL_Z &&
618 swz_z == BRW_CHANNEL_Z &&
670 swz_z == BRW_CHANNEL_Z &&
Dlex.l73 yylval.integer = BRW_CHANNEL_Z;
275 yylval.integer = BRW_CHANNEL_Z;
Dgen8_instruction.c215 BRW_CHANNEL_Z)); in gen8_set_src0()
303 BRW_CHANNEL_Z)); in gen8_set_src1()
Dbrw_disasm.c683 swz_z == BRW_CHANNEL_Z && in src_da16()
732 swz_z == BRW_CHANNEL_Z && in src0_3src()
784 swz_z == BRW_CHANNEL_Z && in src1_3src()
835 swz_z == BRW_CHANNEL_Z && in src2_3src()
Dbrw_defines.h556 #define BRW_CHANNEL_Z 2 macro
Dbrw_eu_emit.c335 insn->bits2.da16.src0_swz_z = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z); in brw_set_src0()
422 insn->bits3.da16.src1_swz_z = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z); in brw_set_src1()
Dgram.y2829 | Z { $$ = 1 << BRW_CHANNEL_Z; }
/external/mesa3d/src/intel/tools/
Di965_lex.l208 <DOTSEL>"z" { yylval.integer = BRW_CHANNEL_Z; return Z; }
247 <CHANNEL>"z" { yylval.integer = BRW_CHANNEL_Z; return Z; }
Di965_gram.y2134 | Z { $$ = 1 << BRW_CHANNEL_Z; }
/external/mesa3d/src/intel/compiler/
Dbrw_eu_defines.h105 #define BRW_CHANNEL_Z 2 macro
Dbrw_eu_emit.c315 BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Z)); in brw_set_src0()
422 BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Z)); in brw_set_src1()
Dbrw_disasm.c957 unsigned z = BRW_GET_SWZ(swiz, BRW_CHANNEL_Z); in src_swizzle()