Searched refs:GPRs (Results 1 – 25 of 133) sorted by relevance
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| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | asm-17.ll | 6 ; Test i32 GPRs.
17 ; Test i64 GPRs.
63 ; Test clobbers of GPRs and CC.
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| D | fp-move-13.ll | 21 ; Test 128-bit moves from GPRs to VRs. i128 isn't a legitimate type,
34 ; Test 128-bit moves from VRs to GPRs, with the same restriction as f2.
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| D | args-08.ll | 5 ; Up to four integer return values fit into GPRs.
32 ; Up to four floating-point return values fit into GPRs.
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| D | fp-move-02.ll | 1 ; Test moves between FPRs and GPRs. The 32-bit cases test the z10
11 ; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high
57 ; Test 64-bit moves from GPRs to FPRs.
65 ; Test 128-bit moves from GPRs to FPRs. i128 isn't a legitimate type,
80 ; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should
90 ; Test 64-bit moves from FPRs to GPRs.
98 ; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
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| D | frame-05.ll | 1 ; Test saving and restoring of call-saved GPRs.
5 ; This function should require all GPRs, but no other spill slots. The caller
81 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs
188 ; This function should use all call-clobbered GPRs but no call-saved ones.
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| D | frame-25.ll | 4 ; where no GPRs are saved / restored.
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| D | int-move-01.ll | 1 ; Test moves between GPRs.
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| D | frame-06.ll | 7 ; This function should require all GPRs, but no other spill slots. The caller
78 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs
185 ; This function should use all call-clobbered GPRs but no call-saved ones.
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | asm-17.ll | 6 ; Test i32 GPRs.
17 ; Test i64 GPRs.
63 ; Test clobbers of GPRs and CC.
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| D | args-08.ll | 5 ; Up to four integer return values fit into GPRs.
32 ; Up to four floating-point return values fit into GPRs.
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| D | fp-move-02.ll | 1 ; Test moves between FPRs and GPRs. The 32-bit cases test the z10
11 ; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high
57 ; Test 64-bit moves from GPRs to FPRs.
65 ; Test 128-bit moves from GPRs to FPRs. i128 isn't a legitimate type,
80 ; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should
90 ; Test 64-bit moves from FPRs to GPRs.
98 ; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
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| D | frame-05.ll | 1 ; Test saving and restoring of call-saved GPRs.
5 ; This function should require all GPRs, but no other spill slots. The caller
81 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs
188 ; This function should use all call-clobbered GPRs but no call-saved ones.
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| D | int-move-01.ll | 1 ; Test moves between GPRs.
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| D | frame-06.ll | 7 ; This function should require all GPRs, but no other spill slots. The caller
78 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs
185 ; This function should use all call-clobbered GPRs but no call-saved ones.
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| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | inlineasm-operand-implicit-cast.ll | 85 ; Check support for returning several floats in GPRs with matching float inputs
98 ; Check support for returning several double in GPRs with matching double input
111 ; Check support for returning several float in specific GPRs with matching
124 ; Check support for returning several double in specific GPRs with matching
235 ; Check support for returning several floats in GPRs with matching float inputs
253 ; Check support for returning several double in GPRs with matching double input
271 ; Check support for returning several float in specific GPRs with matching
289 ; Check support for returning several double in specific GPRs with matching
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| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | Frames-stack-floor.ll | 28 ; 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved);
31 ; 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
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| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | mmx-copy-gprs.ll | 6 ; This test should use GPRs to copy the mmx value, not MMX regs. Using mmx regs,
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| /external/llvm/test/CodeGen/X86/ |
| D | mmx-copy-gprs.ll | 6 ; This test should use GPRs to copy the mmx value, not MMX regs. Using mmx regs,
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| /external/llvm-project/llvm/test/CodeGen/Thumb/ |
| D | 2011-06-16-NoGPRs.ll | 5 ; register, but we cannot have live GPRs in thumb mode because we don't know how
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| /external/llvm/test/CodeGen/Thumb/ |
| D | 2011-06-16-NoGPRs.ll | 5 ; register, but we cannot have live GPRs in thumb mode because we don't know how
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 238 // GPRs without the PC. Some ARM instructions do not allow the PC in
250 // GPRs without the PC but with APSR. Some instructions allow accessing the
261 // GPRs without the PC and SP registers but with APSR. Used by CLRM instruction.
308 // GPRs without the PC and SP but with APSR_NZCV.Some instructions allow
498 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
499 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.
507 // Register class representing a pair of even-odd GPRs.
512 // Register class representing a pair of even-odd GPRs, except (R12, SP).
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | ppc64-align-long-double.ll | 5 ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | framelayout-unaligned-fp.ll | 4 ; of callee-saved GPRs as well as an odd number of callee-saved FPRs are
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| /external/libffi/src/powerpc/ |
| D | darwin_closure.S | 39 ; Define some pseudo-opcodes for size-independent load & store of GPRs ...
45 ; ... and the size of GPRs and their storage indicator.
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| /external/python/cpython2/Modules/_ctypes/libffi/src/powerpc/ |
| D | darwin_closure.S | 39 ; Define some pseudo-opcodes for size-independent load & store of GPRs ...
45 ; ... and the size of GPRs and their storage indicator.
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