| /external/fdlibm/ |
| D | e_log.c | 76 Lg2 = 3.999999999940941908e-01, /* 3FD99999 9997FA04 */ variable
127 t1= w*(Lg2+w*(Lg4+w*Lg6));
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4939 unsigned Lg2 = C.countTrailingZeros(); in selectSDiv() local
4946 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv()
4953 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv()
4983 SelectReg, /*IsKill=*/true, AArch64_AM::ASR, Lg2); in selectSDiv()
4985 ResultReg = emitASR_ri(VT, VT, SelectReg, /*IsKill=*/true, Lg2); in selectSDiv()
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| D | AArch64ISelLowering.cpp | 9707 unsigned Lg2 = Divisor.countTrailingZeros(); in BuildSDIVPow2() local
9709 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSDIVPow2()
9723 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64)); in BuildSDIVPow2()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4760 unsigned Lg2 = C.countTrailingZeros(); in selectSDiv() local
4767 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv()
4774 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv()
4804 SelectReg, /*IsKill=*/true, AArch64_AM::ASR, Lg2); in selectSDiv()
4806 ResultReg = emitASR_ri(VT, VT, SelectReg, /*IsKill=*/true, Lg2); in selectSDiv()
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| D | AArch64ISelLowering.cpp | 7508 unsigned Lg2 = Divisor.countTrailingZeros(); in BuildSDIVPow2() local
7510 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSDIVPow2()
7526 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64)); in BuildSDIVPow2()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4932 unsigned Lg2 = C.countTrailingZeros(); in selectSDiv() local
4939 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv()
4946 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv()
4976 SelectReg, /*IsKill=*/true, AArch64_AM::ASR, Lg2); in selectSDiv()
4978 ResultReg = emitASR_ri(VT, VT, SelectReg, /*IsKill=*/true, Lg2); in selectSDiv()
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| D | AArch64ISelLowering.cpp | 11569 unsigned Lg2 = Divisor.countTrailingZeros(); in BuildSDIVPow2() local
11571 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSDIVPow2()
11585 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64)); in BuildSDIVPow2()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 11217 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros(); in BuildSDIVPow2() local
11218 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT); in BuildSDIVPow2()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 14425 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros(); in BuildSDIVPow2() local
14426 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT); in BuildSDIVPow2()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 15476 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros(); in BuildSDIVPow2() local
15477 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT); in BuildSDIVPow2()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 21036 unsigned Lg2 = Divisor.countTrailingZeros(); in BuildSDIVPow2() local
21039 if (Lg2 == 1) in BuildSDIVPow2()
21045 APInt Lg2Mask = APInt::getLowBitsSet(VT.getSizeInBits(), Lg2); in BuildSDIVPow2()
21059 DAG.getNode(ISD::SRA, DL, VT, CMov, DAG.getConstant(Lg2, DL, MVT::i8)); in BuildSDIVPow2()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 22266 unsigned Lg2 = Divisor.countTrailingZeros(); in BuildSDIVPow2() local
22269 if (Lg2 == 1) in BuildSDIVPow2()
22275 APInt Lg2Mask = APInt::getLowBitsSet(VT.getSizeInBits(), Lg2); in BuildSDIVPow2()
22289 DAG.getNode(ISD::SRA, DL, VT, CMov, DAG.getConstant(Lg2, DL, MVT::i8)); in BuildSDIVPow2()
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| /external/ImageMagick/PerlMagick/t/reference/wmf/ |
| D | wizard.miff | 108 …��^>�}w��oBJ,�W����U�����s`M�����s`M�����s`M�����s`M�����s`M�����s`M����vN��l��Lg2�e���+� .:\��+
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