| /external/capstone/arch/XCore/ |
| D | XCoreDisassembler.c | 629 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
635 S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6); in DecodeL6RInstruction()
640 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL6RInstruction()
670 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
676 S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5); in DecodeL5RInstruction()
681 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL5RInstruction()
692 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction() local
697 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
701 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
712 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstSrcDstInstruction() local
[all …]
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| /external/llvm-project/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 647 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
652 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
656 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL6RInstruction()
681 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
686 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
691 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL5RInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction() local
707 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
710 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
721 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstSrcDstInstruction() local
[all …]
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| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
657 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL6RInstruction()
682 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
692 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL5RInstruction()
703 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction() local
708 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
711 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
722 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstSrcDstInstruction() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 647 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
652 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
656 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL6RInstruction()
681 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
686 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
691 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL5RInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction() local
707 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
710 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
721 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstSrcDstInstruction() local
[all …]
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| /external/rust/crates/grpcio-sys/grpc/include/grpcpp/impl/codegen/ |
| D | call_op_set.h | 850 class Op3 = CallNoOp<3>, class Op4 = CallNoOp<4>,
860 template <class Op1, class Op2, class Op3, class Op4, class Op5, class Op6>
865 public Op4,
919 this->Op4::FinishOp(status); in FinalizeResult()
949 this->Op4::SetHijackingState(&interceptor_methods_); in SetHijackingState()
962 this->Op4::AddOp(ops, &nops); in ContinueFillOpsAfterInterception()
999 this->Op4::SetInterceptionHookPoint(&interceptor_methods_); in RunInterceptors()
1018 this->Op4::SetFinishInterceptionHookPoint(&interceptor_methods_); in RunInterceptorsPostRecv()
|
| D | completion_queue.h | 92 template <class Op1, class Op2, class Op3, class Op4, class Op5, class Op6>
295 template <class Op1, class Op2, class Op3, class Op4, class Op5, class Op6>
|
| /external/rust/crates/grpcio-sys/grpc/spm-cpp-include/grpcpp/impl/codegen/ |
| D | call_op_set.h | 850 class Op3 = CallNoOp<3>, class Op4 = CallNoOp<4>,
860 template <class Op1, class Op2, class Op3, class Op4, class Op5, class Op6>
865 public Op4,
919 this->Op4::FinishOp(status); in FinalizeResult()
949 this->Op4::SetHijackingState(&interceptor_methods_); in SetHijackingState()
962 this->Op4::AddOp(ops, &nops); in ContinueFillOpsAfterInterception()
999 this->Op4::SetInterceptionHookPoint(&interceptor_methods_); in RunInterceptors()
1018 this->Op4::SetFinishInterceptionHookPoint(&interceptor_methods_); in RunInterceptorsPostRecv()
|
| D | completion_queue.h | 92 template <class Op1, class Op2, class Op3, class Op4, class Op5, class Op6>
295 template <class Op1, class Op2, class Op3, class Op4, class Op5, class Op6>
|
| /external/grpc-grpc/include/grpcpp/impl/codegen/ |
| D | call.h | 616 class Op3 = CallNoOp<3>, class Op4 = CallNoOp<4>,
622 public Op4,
631 this->Op4::AddOp(ops, nops); in FillOps()
642 this->Op4::FinishOp(status); in FinalizeResult()
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 3839 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
3841 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
3843 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
3860 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
3872 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
3882 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext()); in MatchAndEmitInstruction()
3903 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
3905 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
3907 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
3924 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4596 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
4598 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
4600 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
4617 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
4629 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
4639 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext()); in MatchAndEmitInstruction()
4660 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
4662 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
4664 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
4681 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
[all …]
|
| /external/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4723 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
4725 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
4727 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
4744 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
4756 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
4766 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext()); in MatchAndEmitInstruction()
4787 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
4789 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
4791 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
4808 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
[all …]
|
| /external/llvm-project/llvm/include/llvm/IR/ |
| D | PatternMatch.h | 2059 const T4 &Op4) {
2061 m_Argument<4>(Op4));
2068 const T4 &Op4, const T5 &Op5) {
2069 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2, Op3, Op4),
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 1305 SDValue Op4 = Node->getOperand(4); in Select() local
1306 Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); in Select()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 1006 SDValue Op3, SDValue Op4);
1008 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 1564 SDValue Op4 = Node->getOperand(4); in Select() local
1566 CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); in Select()
|
| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 1609 SDValue Op4 = Node->getOperand(4); in Select() local
1611 CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); in Select()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2698 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
2710 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
2719 OutOps.push_back(Op4); in SelectInlineAsmMemoryOperand()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 1220 SDValue Op3, SDValue Op4);
1222 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | PatternMatch.h | 1801 const T4 &Op4) {
1803 m_Argument<4>(Op4));
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 1419 SDValue Op3, SDValue Op4);
1421 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | SVEInstrFormats.td | 350 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, vt4:$Op4)),
351 (inst $Op1, $Op2, $Op3, $Op4)>;
367 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, (vt4 ImmTy:$Op4))),
368 (inst $Op1, $Op2, $Op3, ImmTy:$Op4)>;
1739 …def : Pat<(nxv8f16 (op nxv8i1:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, nxv8f16:$Op4, (i32 complexrotateop…
1740 (!cast<Instruction>(NAME # _H) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
1741 …def : Pat<(nxv4f32 (op nxv4i1:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, nxv4f32:$Op4, (i32 complexrotateop…
1742 (!cast<Instruction>(NAME # _S) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
1743 …def : Pat<(nxv2f64 (op nxv2i1:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, nxv2f64:$Op4, (i32 complexrotateop…
1744 (!cast<Instruction>(NAME # _D) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | SVEInstrFormats.td | 370 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, vt4:$Op4)),
371 (inst $Op1, $Op2, $Op3, $Op4)>;
387 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, (vt4 ImmTy:$Op4))),
388 (inst $Op1, $Op2, $Op3, ImmTy:$Op4)>;
1935 …def : Pat<(nxv8f16 (op nxv8i1:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, nxv8f16:$Op4, (i32 complexrotateop…
1936 (!cast<Instruction>(NAME # _H) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
1937 …def : Pat<(nxv4f32 (op nxv4i1:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, nxv4f32:$Op4, (i32 complexrotateop…
1938 (!cast<Instruction>(NAME # _S) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
1939 …def : Pat<(nxv2f64 (op nxv2i1:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, nxv2f64:$Op4, (i32 complexrotateop…
1940 (!cast<Instruction>(NAME # _D) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 5278 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
5286 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
5295 OutOps.push_back(Op4); in SelectInlineAsmMemoryOperand()
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5544 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); in tryConvertingToTwoOperandForm() local
5545 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
5549 auto Op4Reg = Op4.getReg(); in tryConvertingToTwoOperandForm()
5593 LastOp = &Op4; in tryConvertingToTwoOperandForm()
5614 std::swap(Op4, Op5); in tryConvertingToTwoOperandForm()
|