| /external/oboe/samples/RhythmGame/third_party/glm/gtc/ |
| D | bitfield.inl | 22 glm::uint16 REG2(y); local
25 REG2 = ((REG2 << 4) | REG2) & glm::uint16(0x0F0F);
28 REG2 = ((REG2 << 2) | REG2) & glm::uint16(0x3333);
31 REG2 = ((REG2 << 1) | REG2) & glm::uint16(0x5555);
33 return REG1 | (REG2 << 1);
40 glm::uint32 REG2(y); local
43 REG2 = ((REG2 << 8) | REG2) & glm::uint32(0x00FF00FF);
46 REG2 = ((REG2 << 4) | REG2) & glm::uint32(0x0F0F0F0F);
49 REG2 = ((REG2 << 2) | REG2) & glm::uint32(0x33333333);
52 REG2 = ((REG2 << 1) | REG2) & glm::uint32(0x55555555);
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | addze.ll | 10 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
22 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
35 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
48 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
61 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
74 ; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
87 ; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
88 ; CHECK-NEXT: addic [[REG1]], [[REG2]], -1
89 ; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]
90 ; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
[all …]
|
| D | mul-const-vector.ll | 12 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
22 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
23 ; CHECK-NEXT: vaddubm v[[REG3:[0-9]+]], v2, v[[REG2]]
33 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
34 ; CHECK-NEXT: vsububm v[[REG3:[0-9]+]], v[[REG2]], v2
47 ; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],
48 ; CHECK-NEXT: vsububm v[[REG4:[0-9]+]], v[[REG2]], v[[REG3]]
60 ; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],
61 ; CHECK-NEXT: vsububm v[[REG5:[0-9]+]], v[[REG2]], v[[REG4]]
71 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
[all …]
|
| D | bperm.ll | 26 ; CHECK-DAG: rotldi [[REG2:[0-9]+]], 3, 8
28 ; CHECK-DAG: rldimi [[REG2]], [[REG1]], 8, 48
30 ; CHECK-DAG: rldimi [[REG2]], [[REG3]], 16, 40
32 ; CHECK-DAG: rldimi [[REG2]], [[REG4]], 24, 32
34 ; CHECK-DAG: rldimi [[REG2]], [[REG5]], 40, 16
35 ; CHECK-DAG: rldimi [[REG2]], [[REG6]], 48, 8
36 ; CHECK-DAG: rldimi [[REG2]], 3, 56, 0
37 ; CHECK: mr 3, [[REG2]]
50 ; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 19
51 ; CHECK: and 3, [[REG3]], [[REG2]]
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | aarch64-be-bv.ll | 8 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1
9 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
20 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #8
21 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
32 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #16
33 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
44 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #24
45 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
56 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #1
57 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | aarch64-be-bv.ll | 8 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1
9 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
20 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #8
21 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
32 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #16
33 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
44 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #24
45 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
56 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #1
57 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | atomic-64bit.ll | 9 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
11 ; CHECK-LE: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
12 ; CHECK-BE: adds [[REG4:(r[0-9]?[13579])]], [[REG2]]
21 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
23 ; CHECK-THUMB-LE: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
24 ; CHECK-THUMB-BE: adds.w [[REG4:[a-z0-9]+]], [[REG2]]
38 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
40 ; CHECK-LE: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
41 ; CHECK-BE: subs [[REG4:(r[0-9]?[13579])]], [[REG2]]
50 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
[all …]
|
| D | gep-optimization.ll | 12 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
13 ; CHECK-T1: adds r0, r0, [[REG2]]
23 ; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}}
24 ; CHECK: ldr r0, [r0, [[REG2]]]
36 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
37 ; CHECK-T1: adds r0, r0, [[REG2]]
47 ; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}}
48 ; CHECK: ldr r0, [r0, [[REG2]]]
60 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
61 ; CHECK-T1: adds r0, r0, [[REG2]]
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | atomic-64bit.ll | 9 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
11 ; CHECK-LE: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
12 ; CHECK-BE: adds [[REG4:(r[0-9]?[13579])]], [[REG2]]
21 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
23 ; CHECK-THUMB-LE: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
24 ; CHECK-THUMB-BE: adds.w [[REG4:[a-z0-9]+]], [[REG2]]
38 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
40 ; CHECK-LE: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
41 ; CHECK-BE: subs [[REG4:(r[0-9]?[13579])]], [[REG2]]
50 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
[all …]
|
| D | gep-optimization.ll | 12 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
13 ; CHECK-T1: adds r0, r0, [[REG2]]
23 ; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}}
24 ; CHECK: ldr r0, [r0, [[REG2]]]
36 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
37 ; CHECK-T1: adds r0, r0, [[REG2]]
47 ; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}}
48 ; CHECK: ldr r0, [r0, [[REG2]]]
60 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
61 ; CHECK-T1: adds r0, r0, [[REG2]]
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/AVR/ |
| D | call.ll | 34 ; CHECK: ldi [[REG2:r[0-9]+]], 11
36 ; CHECK: std Z+2, [[REG2]]
56 ; CHECK: ldi [[REG2:r[0-9]+]], 2
58 ; CHECK: std Z+2, [[REG2]]
60 ; CHECK: ldi [[REG2:r[0-9]+]], 2
62 ; CHECK: std Z+4, [[REG2]]
86 ; CHECK: ldi [[REG2:r[0-9]+]], 66
88 ; CHECK: std Z+2, [[REG2]]
90 ; CHECK: ldi [[REG2:r[0-9]+]], 2
92 ; CHECK: std Z+4, [[REG2]]
[all …]
|
| D | directmem.ll | 39 ; CHECK: ldi [[REG2:r[0-9]+]], 2
40 ; CHECK: sts char.array+1, [[REG2]]
69 ; CHECK: ldi [[REG2:r[0-9]+]], 170
70 ; CHECK: sts int+1, [[REG2]]
88 ; CHECK: ldi [[REG2:r[0-9]+]], 170
89 ; CHECK: sts int.array+5, [[REG2]]
93 ; CHECK: ldi [[REG2:r[0-9]+]], 170
94 ; CHECK: sts int.array+3, [[REG2]]
98 ; CHECK: ldi [[REG2:r[0-9]+]], 170
99 ; CHECK: sts int.array+1, [[REG2]]
[all …]
|
| /external/llvm/test/CodeGen/X86/ |
| D | lea-opt.ll | 40 ; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]]
44 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
45 ; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
47 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
48 ; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
82 ; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]]
83 ; ENABLED: movl -4([[REG2]]), {{.*}}
84 ; ENABLED: subl ([[REG2]]), {{.*}}
85 ; ENABLED: addl 4([[REG2]]), {{.*}}
89 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
[all …]
|
| /external/llvm/test/FileCheck/ |
| D | check-dag-xfails.txt | 16 ; X1-DAG: add [[REG2:r[0-9]+]], r3, r4
17 ; X1: mul r5, [[REG1]], [[REG2]]
28 ; X2-DAG: mul [[REG2:r[0-9]+]], r3, r4
29 ; X2: add r5, [[REG1]], [[REG2]]
40 ; X3-DAG: add [[REG2:r[0-9]+]], r3, r4
41 ; X3-DAG: mul r5, [[REG1]], [[REG2]]
53 ; X4-DAG: add [[REG2:r[0-9]+]], r3, r4
55 ; X4-DAG: mul r5, [[REG1]], [[REG2]]
67 ; X5-DAG: add [[REG2:r[0-9]+]], r3, r4
69 ; X5-DAG: mul r5, [[REG1]], [[REG2]]
[all …]
|
| /external/llvm-project/llvm/test/FileCheck/ |
| D | check-dag-xfails.txt | 16 ; X1-DAG: add [[REG2:r[0-9]+]], r3, r4
17 ; X1: mul r5, [[REG1]], [[REG2]]
28 ; X2-DAG: mul [[REG2:r[0-9]+]], r3, r4
29 ; X2: add r5, [[REG1]], [[REG2]]
40 ; X3-DAG: add [[REG2:r[0-9]+]], r3, r4
41 ; X3-DAG: mul r5, [[REG1]], [[REG2]]
53 ; X4-DAG: add [[REG2:r[0-9]+]], r3, r4
55 ; X4-DAG: mul r5, [[REG1]], [[REG2]]
67 ; X5-DAG: add [[REG2:r[0-9]+]], r3, r4
69 ; X5-DAG: mul r5, [[REG1]], [[REG2]]
[all …]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | anon_aggr.ll | 33 ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
36 ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
43 ; DARWIN64: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
46 ; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
65 ; CHECK: ld [[REG2:[0-9]+]], 72(1)
66 ; CHECK: cmpld {{([0-9]+,)?}}4, [[REG2]]
67 ; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]]
74 ; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
77 ; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]]
79 ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
[all …]
|
| D | bperm.ll | 26 ; CHECK-DAG: rotldi [[REG2:[0-9]+]], 3, 8
28 ; CHECK-DAG: rldimi [[REG2]], [[REG1]], 8, 48
30 ; CHECK-DAG: rldimi [[REG2]], [[REG3]], 16, 40
32 ; CHECK-DAG: rldimi [[REG2]], [[REG4]], 24, 32
34 ; CHECK-DAG: rldimi [[REG2]], [[REG5]], 40, 16
35 ; CHECK-DAG: rldimi [[REG2]], [[REG6]], 48, 8
36 ; CHECK-DAG: rldimi [[REG2]], 3, 56, 0
37 ; CHECK: mr 3, [[REG2]]
50 ; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 19
51 ; CHECK: and 3, [[REG3]], [[REG2]]
[all …]
|
| D | qpx-s-sel.ll | 28 ; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
30 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
56 ; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
57 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
70 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
71 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
85 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
86 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
101 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
102 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
[all …]
|
| D | qpx-sel.ll | 32 ; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
34 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
60 ; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
61 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
74 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
75 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
89 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
90 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
105 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
106 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | simplestorei.ll | 13 ; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
15 ; CHECK: sw $[[REG1]], 0($[[REG2]])
26 ; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 32768
28 ; CHECK: sw $[[REG2]], 0($[[REG3]])
37 ; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
39 ; CHECK: sw $[[REG1]], 0($[[REG2]])
48 ; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
50 ; CHECK: sw $[[REG1]], 0($[[REG2]])
61 ; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
62 ; CHECK: sw $[[REG1]], 0($[[REG2]])
|
| D | bricmpi1.ll | 42 ; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
43 ; CHECK: bnez $[[REG2]],
60 ; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
61 ; CHECK: beqz $[[REG2]],
78 ; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
79 ; CHECK: bnez $[[REG2]],
95 ; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
96 ; CHECK: beqz $[[REG2]],
112 ; CHECK: negu $[[REG2:[0-9]+]], $[[REG0]]
115 ; CHECK: slt $[[REG4:[0-9]+]], $[[REG3]], $[[REG2]]
[all …]
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | simplestorei.ll | 14 ; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
15 ; CHECK: sw $[[REG1]], 0($[[REG2]])
26 ; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 32768
28 ; CHECK: sw $[[REG2]], 0($[[REG3]])
38 ; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
39 ; CHECK: sw $[[REG1]], 0($[[REG2]])
49 ; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
50 ; CHECK: sw $[[REG1]], 0($[[REG2]])
61 ; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
62 ; CHECK: sw $[[REG1]], 0($[[REG2]])
|
| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | int-usub-08.ll | 13 ; CHECK-DAG: ipm [[REG2:%r[0-5]]]
14 ; CHECK-DAG: afi [[REG2]], -536870912
15 ; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
29 ; CHECK-DAG: ipm [[REG2:%r[0-5]]]
30 ; CHECK-DAG: afi [[REG2]], -536870912
31 ; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
45 ; CHECK-DAG: ipm [[REG2:%r[0-5]]]
46 ; CHECK-DAG: afi [[REG2]], -536870912
47 ; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
61 ; CHECK-DAG: ipm [[REG2:%r[0-5]]]
[all …]
|
| D | stack-guard.ll | 10 ; CHECK: ear [[REG2:%r[1-9][0-9]?]], %a0
11 ; CHECK: sllg [[REG2]], [[REG2]], 32
12 ; CHECK: ear [[REG2]], %a1
13 ; CHECK: lg [[REG2]], 40([[REG2]])
14 ; CHECK: cg [[REG2]], {{[0-9]*}}(%r15)
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | stack-guard.ll | 10 ; CHECK: ear [[REG2:%r[1-9][0-9]?]], %a0
11 ; CHECK: sllg [[REG2]], [[REG2]], 32
12 ; CHECK: ear [[REG2]], %a1
13 ; CHECK: lg [[REG2]], 40([[REG2]])
14 ; CHECK: sg [[REG2]], {{[0-9]*}}(%r15)
|