| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | verify-sop.mir | 3 # CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
6 # CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
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| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 71 SOPC Instructions
73 All SOPC instructions are supported.
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 39 SOPC = 5 variable in Format
469 SOPC = { variable
492 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPC:
493 opcode(name, gfx7, gfx9, gfx10, Format.SOPC)
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| D | aco_ir.h | 76 SOPC = 5, enumerator
930 format == Format::SOPC || in isSALU()
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| D | aco_assembler.cpp | 151 case Format::SOPC: { in emit_instruction()
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| D | aco_validate.cpp | 239 instr->format == Format::SOPC || in validate_ir()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 27 field bits<1> SOPC = 0;
63 let TSFlags{7} = SOPC;
305 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
312 let SOPC = 1;
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| D | SIDefines.h | 24 SOPC = 1 << 7, enumerator
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| D | SIInstrInfo.h | 224 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
228 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
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| D | SIInstructions.td | 326 // SOPC Instructions
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| D | SIInstrInfo.td | 871 string opName, list<dag> pattern = []> : SOPC <
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 23 field bit SOPC = 0;
144 let TSFlags{4} = SOPC;
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| D | SIDefines.h | 27 SOPC = 1 << 4, enumerator
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| D | SIInstrInfo.h | 380 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
384 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
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| D | SOPInstructions.td | 930 // SOPC Instructions
940 let SOPC = 1;
1769 // SOPC - GFX6, GFX7, GFX8, GFX9, GFX10
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 23 field bit SOPC = 0;
136 let TSFlags{4} = SOPC;
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| D | SIDefines.h | 27 SOPC = 1 << 4, enumerator
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| D | SOPInstructions.td | 835 // SOPC Instructions
848 class SOPC <bits<7> op, dag outs, dag ins, string asm,
855 let SOPC = 1;
863 string opName, list<dag> pattern = []> : SOPC <
923 def S_SET_GPR_IDX_ON : SOPC <0x11,
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| D | SIInstrInfo.h | 374 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
378 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 3341 if (!(Desc.TSFlags & (SIInstrFlags::SOP2 | SIInstrFlags::SOPC))) in validateSOPLiteral()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 3716 if (!(Desc.TSFlags & (SIInstrFlags::SOP2 | SIInstrFlags::SOPC))) in validateSOPLiteral()
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| /external/llvm-project/llvm/docs/AMDGPU/ |
| D | AMDGPUAsmGFX7.rst | 549 SOPC section in Instructions
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| D | AMDGPUAsmGFX8.rst | 572 SOPC section in Instructions
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| D | AMDGPUAsmGFX9.rst | 744 SOPC section in Instructions
|
| /external/llvm-project/llvm/docs/ |
| D | AMDGPUUsage.rst | 8824 SOPC subsubsection
8834 For full list of supported instructions, refer to "SOPC Instructions" in ISA
|