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/external/llvm-project/clang/include/clang/Basic/
DBuiltinsHexagonDep.def12 // V5 Scalar Instructions.
14 TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpeq, "iii", "", V5)
15 TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpgt, "iii", "", V5)
16 TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpgtu, "iii", "", V5)
17 TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpeqp, "iLLiLLi", "", V5)
18 TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpgtp, "iLLiLLi", "", V5)
19 TARGET_BUILTIN(__builtin_HEXAGON_C2_cmpgtup, "iLLiLLi", "", V5)
20 TARGET_BUILTIN(__builtin_HEXAGON_A4_rcmpeqi, "iiIi", "", V5)
21 TARGET_BUILTIN(__builtin_HEXAGON_A4_rcmpneqi, "iiIi", "", V5)
22 TARGET_BUILTIN(__builtin_HEXAGON_A4_rcmpeq, "iii", "", V5)
[all …]
DBuiltinsHexagon.def32 #pragma push_macro("V5")
33 #define V5 "v5|" V55
49 TARGET_BUILTIN(__builtin_SI_to_SXTHI_asrh, "ii", "", V5)
50 TARGET_BUILTIN(__builtin_brev_ldd, "v*LLi*CLLi*iC", "", V5)
51 TARGET_BUILTIN(__builtin_brev_ldw, "v*i*Ci*iC", "", V5)
52 TARGET_BUILTIN(__builtin_brev_ldh, "v*s*Cs*iC", "", V5)
53 TARGET_BUILTIN(__builtin_brev_lduh, "v*Us*CUs*iC", "", V5)
54 TARGET_BUILTIN(__builtin_brev_ldb, "v*Sc*CSc*iC", "", V5)
55 TARGET_BUILTIN(__builtin_brev_ldub, "v*Uc*CUc*iC", "", V5)
56 TARGET_BUILTIN(__builtin_circ_ldd, "LLi*LLi*LLi*iIi", "", V5)
[all …]
/external/icu/icu4c/source/test/testdata/
DIdnaTestV2.txt125 ̈.א; ; [B1, B3, B6, V5]; xn--ssa.xn--4db; ; ; # ̈.א
126 xn--ssa.xn--4db; ̈.א; [B1, B3, B6, V5]; xn--ssa.xn--4db; ; ; # ̈.א
158 ̈‌̈بb; ; [B1, C1, V5]; xn--b-bcba413a2w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
159 ̈‌̈بB; ̈‌̈بb; [B1, C1, V5]; xn--b-bcba413a2w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
160 xn--b-bcba413a; ̈̈بb; [B1, V5]; xn--b-bcba413a; ; ; # ̈̈بb
161 xn--b-bcba413a2w8b; ̈‌̈بb; [B1, C1, V5]; xn--b-bcba413a2w8b; ; ; # ̈̈بb
179 ̈‍̈بb; ; [B1, C2, V5]; xn--b-bcba413a7w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
180 ̈‍̈بB; ̈‍̈بb; [B1, C2, V5]; xn--b-bcba413a7w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
181 xn--b-bcba413a7w8b; ̈‍̈بb; [B1, C2, V5]; xn--b-bcba413a7w8b; ; ; # ̈̈بb
433 a.b.̈c.d; ; [V5]; a.b.xn--c-bcb.d; ; ; # a.b.̈c.d
[all …]
/external/rust/crates/idna/tests/
DIdnaTestV2.txt125 ̈.א; ; [B1, B3, B6, V5]; xn--ssa.xn--4db; ; ; # ̈.א
126 xn--ssa.xn--4db; ̈.א; [B1, B3, B6, V5]; xn--ssa.xn--4db; ; ; # ̈.א
158 ̈‌̈بb; ; [B1, C1, V5]; xn--b-bcba413a2w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
159 ̈‌̈بB; ̈‌̈بb; [B1, C1, V5]; xn--b-bcba413a2w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
160 xn--b-bcba413a; ̈̈بb; [B1, V5]; xn--b-bcba413a; ; ; # ̈̈بb
161 xn--b-bcba413a2w8b; ̈‌̈بb; [B1, C1, V5]; xn--b-bcba413a2w8b; ; ; # ̈̈بb
179 ̈‍̈بb; ; [B1, C2, V5]; xn--b-bcba413a7w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
180 ̈‍̈بB; ̈‍̈بb; [B1, C2, V5]; xn--b-bcba413a7w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
181 xn--b-bcba413a7w8b; ̈‍̈بb; [B1, C2, V5]; xn--b-bcba413a7w8b; ; ; # ̈̈بb
433 a.b.̈c.d; ; [V5]; a.b.xn--c-bcb.d; ; ; # a.b.̈c.d
[all …]
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/data/unicode/
DIdnaTestV2.txt125 ̈.א; ; [B1, B3, B6, V5]; xn--ssa.xn--4db; ; ; # ̈.א
126 xn--ssa.xn--4db; ̈.א; [B1, B3, B6, V5]; xn--ssa.xn--4db; ; ; # ̈.א
158 ̈‌̈بb; ; [B1, C1, V5]; xn--b-bcba413a2w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
159 ̈‌̈بB; ̈‌̈بb; [B1, C1, V5]; xn--b-bcba413a2w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
160 xn--b-bcba413a; ̈̈بb; [B1, V5]; xn--b-bcba413a; ; ; # ̈̈بb
161 xn--b-bcba413a2w8b; ̈‌̈بb; [B1, C1, V5]; xn--b-bcba413a2w8b; ; ; # ̈̈بb
179 ̈‍̈بb; ; [B1, C2, V5]; xn--b-bcba413a7w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
180 ̈‍̈بB; ̈‍̈بb; [B1, C2, V5]; xn--b-bcba413a7w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
181 xn--b-bcba413a7w8b; ̈‍̈بb; [B1, C2, V5]; xn--b-bcba413a7w8b; ; ; # ̈̈بb
433 a.b.̈c.d; ; [V5]; a.b.xn--c-bcb.d; ; ; # a.b.̈c.d
[all …]
/external/icu/android_icu4j/src/main/tests/android/icu/dev/data/unicode/
DIdnaTestV2.txt125 ̈.א; ; [B1, B3, B6, V5]; xn--ssa.xn--4db; ; ; # ̈.א
126 xn--ssa.xn--4db; ̈.א; [B1, B3, B6, V5]; xn--ssa.xn--4db; ; ; # ̈.א
158 ̈‌̈بb; ; [B1, C1, V5]; xn--b-bcba413a2w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
159 ̈‌̈بB; ̈‌̈بb; [B1, C1, V5]; xn--b-bcba413a2w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
160 xn--b-bcba413a; ̈̈بb; [B1, V5]; xn--b-bcba413a; ; ; # ̈̈بb
161 xn--b-bcba413a2w8b; ̈‌̈بb; [B1, C1, V5]; xn--b-bcba413a2w8b; ; ; # ̈̈بb
179 ̈‍̈بb; ; [B1, C2, V5]; xn--b-bcba413a7w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
180 ̈‍̈بB; ̈‍̈بb; [B1, C2, V5]; xn--b-bcba413a7w8b; ; xn--b-bcba413a; [B1, V5] # ̈̈بb
181 xn--b-bcba413a7w8b; ̈‍̈بb; [B1, C2, V5]; xn--b-bcba413a7w8b; ; ; # ̈̈بb
433 a.b.̈c.d; ; [V5]; a.b.xn--c-bcb.d; ; ; # a.b.̈c.d
[all …]
/external/llvm/test/CodeGen/Thumb/
Dldr_ext.ll1 ; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=V5
7 ; V5: ldrb
16 ; V5: ldrh
25 ; V5: ldrb
26 ; V5: lsls
27 ; V5: asrs
37 ; V5: ldrh
38 ; V5: lsls
39 ; V5: asrs
49 ; V5: movs r0, #0
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb/
Dldr_ext.ll1 ; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=V5
7 ; V5: ldrb
16 ; V5: ldrh
25 ; V5: ldrb
26 ; V5: lsls
27 ; V5: asrs
37 ; V5: ldrh
38 ; V5: lsls
39 ; V5: asrs
49 ; V5: movs r0, #0
[all …]
/external/libxaac/decoder/armv8/
Dixheaacd_sbr_imdct_using_fft.s108 LD2 {V4.S, V5.S}[0], [X5], X1
119 LD2 {V4.S, V5.S}[1], [X6] , X1
131 LD2 {V4.S, V5.S}[2], [X7] , X1
138 LD2 {V4.S, V5.S}[3], [X11] , X1
152 ADD V0.4S, V1.4S, V5.4S
156 SUB V4.4S, V1.4S, V5.4S
172 SUB V5.4S, V2.4S, V6.4S
189 SUB V6.4S, V4.4S, V5.4S
192 ADD V9.4S, V4.4S, V5.4S
198 SUB V5.4S, V8.4S, V1.4S
[all …]
Dixheaacd_overlap_add2.s72 REV64 V5.4H, V7.4H
84 SMLSL V23.4S, V5.4H, V3.4H
103 REV64 V5.4H, V7.4H
114 SMLSL V23.4S, V5.4H, V3.4H
196 LD2 {V4.4H, V5.4H}, [X1], #16
202 SMLSL V23.4S, V5.4H, V2.4H
217 SMLSL V23.4S, V5.4H, V2.4H
245 LD2 {V4.4H, V5.4H}, [X1], #16
260 SMLSL V23.4S, V5.4H, V2.4H
/external/eigen/unsupported/Eigen/CXX11/src/Tensor/
DTensorDimensions.h154 template <std::size_t V1=0, std::size_t V2=0, std::size_t V3=0, std::size_t V4=0, std::size_t V5=0>…
155 …ro_size<V3>::type, typename non_zero_size<V4>::type, typename non_zero_size<V5>::type >::type Base;
224 template <std::size_t V1, std::size_t V2, std::size_t V3, std::size_t V4, std::size_t V5>
225 EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE std::size_t array_prod(const Sizes<V1, V2, V3, V4, V5>&) {
226 return Sizes<V1, V2, V3, V4, V5>::total_size;
385 …e_t V2, std::size_t V3, std::size_t V4, std::size_t V5> struct array_size<const Sizes<V1,V2,V3,V4,…
386 static const size_t value = Sizes<V1,V2,V3,V4,V5>::count;
388 …size_t V2, std::size_t V3, std::size_t V4, std::size_t V5> struct array_size<Sizes<V1,V2,V3,V4,V5>…
389 static const size_t value = Sizes<V1,V2,V3,V4,V5>::count;
391 …3, std::size_t V4, std::size_t V5> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE std::size_t array_get(con…
[all …]
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/
DPhiEliminate2.ll13 %V5 = sext i16 %V3 to i32
16 %V6 = phi i32 [ %V5, %else ], [ %V4, %then ]
22 ; CHECK-NEXT: %V5 = sext i16 %V3 to i32
24 ; CHECK-NEXT: %V6 = select i1 %C, i32 %V4, i32 %V5, !prof !0, !unpredictable !1
/external/llvm/test/Transforms/SimplifyCFG/
DPhiEliminate2.ll13 %V5 = sext i16 %V3 to i32
16 %V6 = phi i32 [ %V5, %else ], [ %V4, %then ]
22 ; CHECK-NEXT: %V5 = sext i16 %V3 to i32
24 ; CHECK-NEXT: %V6 = select i1 %C, i32 %V4, i32 %V5, !prof !0, !unpredictable !1
/external/llvm-project/clang/test/CodeGenObjC/
Dos_log.m33 // CHECK: %[[V5:.*]] = bitcast %{{.*}}* %[[V4]] to i8*
34 // CHECK: %[[V6:.*]] = call i8* @llvm.objc.retain(i8* %[[V5]])
79 // CHECK: %[[V5:.*]] = call i8* @llvm.objc.retain(i8* %[[V4]])
80 // CHECK: store i8* %[[V5]], i8** %[[OS_LOG_ARG]], align 8
81 // CHECK: %[[V6:.*]] = ptrtoint i8* %[[V5]] to i64
86 // CHECK-O2: call void (...) @llvm.objc.clang.arc.use(i8* %[[V5]])
102 // CHECK: %[[V5:.*]] = call i8* @llvm.objc.retain(i8* %[[V4]])
103 // CHECK: store i8* %[[V5]], i8** %[[OS_LOG_ARG]], align 8
104 // CHECK: %[[V6:.*]] = ptrtoint i8* %[[V5]] to i64
117 // CHECK-O2: call void (...) @llvm.objc.clang.arc.use(i8* %[[V5]])
Dstrong-in-c-struct.m187 // CHECK: %[[V5:.*]] = bitcast i8** %[[V1]] to i8*
188 // CHECK: %[[V6:.*]] = getelementptr inbounds i8, i8* %[[V5]], i64 24
216 // CHECK: %[[V5:.*]] = getelementptr inbounds i8, i8* %[[V4]], i64 16
217 // CHECK: %[[V6:.*]] = bitcast i8* %[[V5]] to i8**
240 // CHECK: %[[V5:.*]] = bitcast i8** %[[V1]] to i8*
241 // CHECK: %[[V6:.*]] = getelementptr inbounds i8, i8* %[[V5]], i64 24
272 // CHECK: %[[V5:.*]] = bitcast i8** %[[V1]] to i8*
273 // CHECK: %[[V6:.*]] = getelementptr inbounds i8, i8* %[[V5]], i64 24
298 // CHECK: %[[V5:.*]] = bitcast i8** %[[V1]] to i8*
299 // CHECK: %[[V6:.*]] = getelementptr inbounds i8, i8* %[[V5]], i64 24
[all …]
/external/llvm/unittests/Support/
DAlignOfTest.cpp70 struct V5 : V4, V3 { double z; argument
71 ~V5() override;
77 struct V8 : V5, virtual V6, V7 { double zz;
87 V5::~V5() {} in ~V5()
149 [AlignOf<V5>::Alignment > 0]
189 EXPECT_LE(alignOf<V1>(), alignOf<V5>()); in TEST()
271 EXPECT_EQ(alignOf<V5>(), alignOf<AlignedCharArrayUnion<V5> >()); in TEST()
336 EXPECT_EQ(sizeof(V5), sizeof(AlignedCharArrayUnion<V5>)); in TEST()
/external/llvm-project/llvm/test/CodeGen/ARM/
Ddebugtrap.ll5 ; RUN: llc < %s -mtriple=armv5 -O0 -filetype=asm | FileCheck --check-prefixes=CHECK,V5 %s
7 ; RUN: llc < %s -mtriple=thumbv5 -O0 -filetype=asm | FileCheck --check-prefixes=CHECK,V5 %s
16 ; V5-NEXT: bkpt #0
DMachO-subtypes.ll7 ; RUN: | llvm-readobj --file-headers - | FileCheck %s --check-prefix=CHECK-V5
9 ; RUN: | llvm-readobj --file-headers - | FileCheck %s --check-prefix=CHECK-V5
11 ; RUN: | llvm-readobj --file-headers - | FileCheck %s --check-prefix=CHECK-V5
13 ; RUN: | llvm-readobj --file-headers - | FileCheck %s --check-prefix=CHECK-V5
15 ; RUN: | llvm-readobj --file-headers - | FileCheck %s --check-prefix=CHECK-V5
61 ; CHECK-V5: CpuSubType: CPU_SUBTYPE_ARM_V5 (0x7)
Dpr18364-movw.ll1 ; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V5
9 ; V5-NOT: movw
25 ; V5-NOT: movw
/external/llvm/test/CodeGen/ARM/
DMachO-subtypes.ll7 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
9 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
11 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
13 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
15 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
61 ; CHECK-V5: CpuSubType: CPU_SUBTYPE_ARM_V5 (0x7)
Dpr18364-movw.ll1 ; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V5
9 ; V5-NOT: movw
25 ; V5-NOT: movw
/external/llvm/lib/Target/Hexagon/
DHexagonSubtarget.h42 V4, V5, V55, V60 enumerator
90 bool hasV5TOps() const { return getHexagonArchVersion() >= V5; } in hasV5TOps()
91 bool hasV5TOpsOnly() const { return getHexagonArchVersion() == V5; } in hasV5TOpsOnly()
/external/llvm/test/MC/AArch64/
Dcase-insen-reg-names.s4 fadd V0.2d, V5.2d, V6.2d
5 fadd v0.2d, V5.2d, v6.2d
/external/llvm-project/llvm/test/MC/AArch64/
Dcase-insen-reg-names.s4 fadd V0.2d, V5.2d, V6.2d
5 fadd v0.2d, V5.2d, v6.2d
/external/llvm-project/mlir/test/Dialect/SCF/
Dparallel-loop-tiling.mlir25 // CHECK: [[V5:%.*]] = affine.min #map([[V1]], [[ARG3]], [[V3]])
27 // CHECK: scf.parallel ([[V7:%.*]], [[V8:%.*]]) = ([[C0]], [[C0]]) to ([[V5]], [[V6]]) …
61 // CHECK: scf.parallel ([[V5:%.*]], [[V6:%.*]]) = ([[C0_1]], [[C0_1]]) to ([[V1]], [[V2…
62 // CHECK: = addi [[V5]], [[V3]] : index
93 // CHECK: scf.parallel ([[V5:%.*]], [[V6:%.*]]) = ([[C0]], [[C0]]) to ([[C2]], [[C2]]) …
96 // CHECK: = addi [[V8]], [[V5]] : index

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