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/external/llvm-project/llvm/test/MC/Hexagon/
Dhvx-swapped-regpairs.s2 …cpu=hexagonv65 -mhvx -filetype=asm %s 2>%t; FileCheck --check-prefix=CHECK-V65 --implicit-check-no…
9 # CHECK-V65: error: register pair `WR0' is not permitted for this architecture
19 # CHECK-V65: error: register pair `WR0' is not permitted for this architecture
33 # CHECK-V65: error: register pair `WR0' is not permitted for this architecture
43 # CHECK-V65: error: register pair `WR1' is not permitted for this architecture
DJ2_trap1_dep.s2 …nv65 -filetype=obj %s | llvm-objdump --mcpu=hexagonv65 -d - | FileCheck %s --check-prefix=CHECK-V65
5 # CHECK-V65: trap1(r0,#0)
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonDepArch.h21 enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67 }; enumerator
41 {"hexagonv65", Hexagon::ArchEnum::V65},
DHexagonDepArch.td19 …btargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexagon V65 architec…
DHexagonSubtarget.h165 return getHexagonArchVersion() >= Hexagon::ArchEnum::V65; in hasV65Ops()
168 return getHexagonArchVersion() == Hexagon::ArchEnum::V65; in hasV65OpsOnly()
207 return HexagonHVXVersion >= Hexagon::ArchEnum::V65; in useHVXV65Ops()
DHexagonScheduleV65.td38 // Hexagon V65 Resource Definitions -
DHexagon.td42 "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
DHexagonDepMapAsm2Intrin.td1713 // V65 Scalar Instructions.
3190 // V65 HVX Instructions.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepArch.td13 …btargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexagon V65 architec…
DHexagonDepArch.h16 enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66 }; enumerator
DHexagonSubtarget.h149 return getHexagonArchVersion() >= Hexagon::ArchEnum::V65; in hasV65Ops()
152 return getHexagonArchVersion() == Hexagon::ArchEnum::V65; in hasV65OpsOnly()
DHexagonScheduleV65.td38 // Hexagon V65 Resource Definitions -
DHexagonSchedule.td83 // V65 Machine Info +
DHexagonSubtarget.cpp99 {"hexagonv65", Hexagon::ArchEnum::V65}, in initializeSubtargetDependencies()
DHexagon.td39 "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
DHexagonDepMapAsm2Intrin.td1734 // V65 Scalar Instructions.
3200 // V65 HVX Instructions.
/external/llvm-project/clang/include/clang/Basic/
DBuiltinsHexagon.def24 #pragma push_macro("V65")
25 #define V65 "v65|" V66
27 #define V62 "v62|" V65
131 #pragma pop_macro("V65")
DBuiltinsHexagonDep.def883 // V65 Scalar Instructions.
885 TARGET_BUILTIN(__builtin_HEXAGON_A6_vcmpbeq_notany, "iLLiLLi", "", V65)
1629 // V65 HVX Instructions.
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dswp-check-offset.ll3 …nv65 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck --check-prefix=CHECK-V65 %s
15 ; CHECK-V65: }{{[ \t]*}}:mem_noshuf
/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Dbitcount-128b.ll64 ; CHECK: v[[V65:[0-9]+]].b = vsub(v0.b,v[[V63]].b)
65 ; CHECK: v[[V66:[0-9]+]] = vand(v[[V61]],v[[V65]])
Dbitcount-64b.ll64 ; CHECK: v[[V65:[0-9]+]].b = vsub(v0.b,v[[V63]].b)
65 ; CHECK: v[[V66:[0-9]+]] = vand(v[[V61]],v[[V65]])
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCTargetDesc.cpp82 clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
293 case Hexagon::ArchEnum::V65: in selectHexagonFS()
/external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCTargetDesc.cpp88 clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
357 case Hexagon::ArchEnum::V65: in selectHexagonFS()
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsicsHexagonDep.td3674 // V65 Scalar Instructions.
5877 // V65 HVX Instructions.
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsHexagon.td3987 // V65 Scalar Instructions.
6176 // V65 HVX Instructions.