| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_bo.c | 68 size = align64(size, getpagesize()); in radv_amdgpu_bo_va_op()
314 -align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_destroy()
317 -align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_destroy()
323 -align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_destroy()
477 align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_create()
480 align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_create()
486 align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_create()
593 align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_from_ptr()
670 align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_from_fd()
673 align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_from_fd()
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| /external/mesa3d/src/util/ |
| D | blob.c | 88 const size_t new_size = align64(blob->size, alignment); in align_blob()
105 blob->current = blob->data + align64(blob->current - blob->data, alignment); in align_blob_reader()
215 assert(align64((_offset), (_align)) == (_offset)) in BLOB_WRITE_TYPE()
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| D | ralloc.c | 133 void *block = malloc(align64(size + sizeof(ralloc_header), in ralloc_size()
181 info = realloc(old, align64(size + sizeof(ralloc_header), in resize()
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| D | u_math.h | 739 align64(uint64_t value, unsigned alignment) in align64() function
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| D | register_allocate.c | 526 alloc = align64(alloc, BITSET_WORDBITS); in ra_realloc_interference_graph()
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| /external/mesa3d/src/intel/common/ |
| D | gen_aux_map.c | 155 uint64_t aligned = align64(gpu, align); in align_and_verify_space()
457 assert(align64(address, GEN_AUX_MAP_MAIN_PAGE_SIZE) == address); in gen_aux_map_add_mapping()
458 assert(align64(aux_address, GEN_AUX_MAP_AUX_PAGE_SIZE) == aux_address); in gen_aux_map_add_mapping()
533 assert(align64(address, GEN_AUX_MAP_MAIN_PAGE_SIZE) == address); in gen_aux_map_unmap_range()
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| /external/mesa3d/src/intel/tools/ |
| D | intel_sanitize_gpu.c | 168 .offset = align64(bo_size(fd, handle), 4096), in padding_is_good()
212 create->size = align64(original_size, 4096) + PADDING_SIZE; in create_with_padding()
222 .offset = align64(create->size, 4096), in create_with_padding()
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| /external/mesa3d/src/mapi/glapi/gen/ |
| D | glX_proto_recv.py | 241 align64 = 0
251 align64 = 1
297 if align64:
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| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_bo.c | 217 ws->allocated_vram -= align64(bo->base.size, ws->info.gart_page_size); in amdgpu_bo_destroy()
219 ws->allocated_gtt -= align64(bo->base.size, ws->info.gart_page_size); in amdgpu_bo_destroy()
586 ws->allocated_vram += align64(size, ws->info.gart_page_size); in amdgpu_create_bo()
588 ws->allocated_gtt += align64(size, ws->info.gart_page_size); in amdgpu_create_bo()
1086 map_size = align64(size, RADEON_SPARSE_PAGE_SIZE); in amdgpu_bo_sparse_create()
1352 size = align64(size, ws->info.gart_page_size); in amdgpu_bo_create()
1497 ws->allocated_vram += align64(bo->base.size, ws->info.gart_page_size); in amdgpu_bo_from_handle()
1499 ws->allocated_gtt += align64(bo->base.size, ws->info.gart_page_size); in amdgpu_bo_from_handle()
1604 uint64_t aligned_size = align64(size, ws->info.gart_page_size); in amdgpu_bo_from_ptr()
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| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_surface.c | 442 surf_ws->htile_offset = align64(surf_ws->total_size, surf_ws->htile_alignment); in radeon_winsys_surface_init()
448 surf_ws->fmask_offset = align64(surf_ws->total_size, surf_ws->fmask_alignment); in radeon_winsys_surface_init()
454 surf_ws->cmask_offset = align64(surf_ws->total_size, surf_ws->cmask_alignment); in radeon_winsys_surface_init()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_sqtt.c | 43 data_offset = align64(sizeof(struct radv_thread_trace_info) * 4, in radv_thread_trace_get_data_offset()
503 device->thread_trace_buffer_size = align64(device->thread_trace_buffer_size, in radv_thread_trace_init_bo()
507 size = align64(sizeof(struct radv_thread_trace_info) * 4, in radv_thread_trace_init_bo()
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| D | radv_image.c | 1272 surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment); in radv_image_alloc_single_sample_cmask()
1493 image->size = align64(image->size, image->alignment); in radv_image_create()
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| D | radv_device.c | 5482 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment); in radv_GetBufferMemoryRequirements()
6592 align64(buffer->size, 4096), in radv_CreateBuffer()
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| /external/mesa3d/src/amd/common/ |
| D | ac_surface.c | 539 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign); in gfx6_compute_level()
1189 surf->dcc_size = align64(surf->surf_size >> 8, surf->dcc_alignment * 4); in gfx6_compute_surface()
2116 surf->htile_offset = align64(surf->total_size, surf->htile_alignment); in ac_compute_surface()
2123 surf->fmask_offset = align64(surf->total_size, surf->fmask_alignment); in ac_compute_surface()
2130 surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment); in ac_compute_surface()
2146 surf->display_dcc_offset = align64(surf->total_size, surf->u.gfx9.display_dcc_alignment); in ac_compute_surface()
2150 surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment); in ac_compute_surface()
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| D | ac_rtld.c | 156 total_size = align64(total_size, s->align); in layout_symbols()
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| D | ac_gpu_info.c | 107 return align64(size, 256 * 1024 * 1024); in fix_vram_size()
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| /external/mesa3d/src/broadcom/vulkan/ |
| D | v3dv_device.c | 1828 align64(buffer->size, pMemoryRequirements->alignment); in v3dv_GetBufferMemoryRequirements()
1880 const VkDeviceSize aligned_size = align64(buffer->size, buffer->alignment); in v3dv_CreateBuffer()
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| /external/mesa3d/docs/relnotes/ |
| D | 12.0.2.rst | 286 - gallium/util: fix align64
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_texture.c | 666 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment); in r600_texture_allocate_fmask()
709 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment); in r600_texture_allocate_cmask()
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| /external/mesa3d/src/freedreno/vulkan/ |
| D | tu_device.c | 1546 .size = align64(buffer->size, 64), in tu_GetBufferMemoryRequirements2()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_texture.c | 1357 plane_offset[i] = align64(total_size, surface[i].surf_alignment); in si_texture_create()
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| /external/mesa3d/src/gallium/drivers/iris/ |
| D | iris_state.c | 5328 assert(base_addr != 0 && align64(base_addr, 32 * 1024) == base_addr); in init_aux_map_state()
|