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Searched refs:bank_swizzle (Results 1 – 25 of 26) sorted by relevance

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/external/mesa3d/src/gallium/drivers/r600/
Dr700_asm.c62 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle); in r700_bytecode_alu_build()
73 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | in r700_bytecode_alu_build()
97 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1); in r700_bytecode_alu_read()
98 if (alu->bank_swizzle) in r700_bytecode_alu_read()
99 alu->bank_swizzle_force = alu->bank_swizzle; in r700_bytecode_alu_read()
Dr600_asm.c468 struct alu_bank_swizzle *bs, int bank_swizzle) in check_vector() argument
477 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src]; in check_vector()
498 struct alu_bank_swizzle *bs, int bank_swizzle) in check_scalar() argument
524 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src]; in check_scalar()
535 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src]; in check_scalar()
547 int bank_swizzle[5]; in check_and_set_bank_swizzle() local
555 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force; in check_and_set_bank_swizzle()
571 bank_swizzle[i] = SQ_ALU_VEC_012; in check_and_set_bank_swizzle()
573 bank_swizzle[i] = slots[i]->bank_swizzle; in check_and_set_bank_swizzle()
575 bank_swizzle[4] = SQ_ALU_SCL_210; in check_and_set_bank_swizzle()
[all …]
Deg_asm.c298 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | in eg_bytecode_alu_build()
316 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle); in eg_bytecode_alu_build()
327 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | in eg_bytecode_alu_build()
Dr600_asm.h64 unsigned bank_swizzle; member
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_sched.cpp233 unsigned bs = n->bc.bank_swizzle; in unreserve()
261 unsigned bs = n->bc.bank_swizzle; in try_reserve()
495 n->bc.bank_swizzle = 0; in try_reserve()
498 n->bc.bank_swizzle = VEC_210; in try_reserve()
508 n->bc.bank_swizzle = bs; in try_reserve()
529 save_bs[i] = a->bc.bank_swizzle; in try_reserve()
533 a->bc.bank_swizzle = VEC_210; in try_reserve()
540 a->bc.bank_swizzle = 0; in try_reserve()
563 sblog << " bs: trying s" << i << " bs:" << a->bc.bank_swizzle in try_reserve()
569 sblog << " bs: reserved s" << i << " bs:" << a->bc.bank_swizzle in try_reserve()
[all …]
Dsb_bc_builder.cpp399 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
426 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
444 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
459 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
473 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
489 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
Dsb_bc_dump.cpp398 if (n.bc.bank_swizzle) { in dump()
401 s << " " << scl_bs[n.bc.bank_swizzle]; in dump()
403 s << " " << vec_bs[n.bc.bank_swizzle]; in dump()
Dsb_bc.h380 enum bank_swizzle { enum
520 unsigned bank_swizzle:3; member
551 bank_swizzle = 0; in clear()
Dsb_bc_decoder.cpp327 bc.bank_swizzle = iw1.get_BANK_SWIZZLE(); in decode_alu()
349 bc.bank_swizzle = w1.get_BANK_SWIZZLE(); in decode_alu()
366 bc.bank_swizzle = w1.get_BANK_SWIZZLE(); in decode_alu()
385 bc.bank_swizzle = w1.get_BANK_SWIZZLE(); in decode_alu()
/external/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td107 bits<3> bank_swizzle;
114 let Word1{20-18} = bank_swizzle;
165 bits<3> bank_swizzle;
173 let Word1{20-18} = bank_swizzle;
DR600Packetizer.cpp306 AMDGPU::OpName::bank_swizzle); in addToPacket()
310 TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::bank_swizzle); in addToPacket()
DEvergreenInstructions.td415 let bank_swizzle = 0;
465 BANK_SWIZZLE:$bank_swizzle),
487 BANK_SWIZZLE:$bank_swizzle),
519 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
DR600Instructions.td99 BANK_SWIZZLE:$bank_swizzle),
103 "$pred_sel $bank_swizzle"),
142 BANK_SWIZZLE:$bank_swizzle),
147 "$pred_sel $bank_swizzle"),
183 BANK_SWIZZLE:$bank_swizzle),
189 "$bank_swizzle"),
440 let bank_swizzle = 5;
444 let bank_swizzle = 5;
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td116 bits<3> bank_swizzle;
123 let Word1{20-18} = bank_swizzle;
174 bits<3> bank_swizzle;
182 let Word1{20-18} = bank_swizzle;
DR600Packetizer.cpp303 R600::OpName::bank_swizzle); in addToPacket()
307 TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle); in addToPacket()
DR600Instructions.td109 BANK_SWIZZLE:$bank_swizzle),
113 "$pred_sel $bank_swizzle"),
152 BANK_SWIZZLE:$bank_swizzle),
157 "$pred_sel $bank_swizzle"),
193 BANK_SWIZZLE:$bank_swizzle),
199 "$bank_swizzle"),
453 let bank_swizzle = 5;
457 let bank_swizzle = 5;
DEvergreenInstructions.td600 let bank_swizzle = 0;
645 BANK_SWIZZLE:$bank_swizzle),
667 BANK_SWIZZLE:$bank_swizzle),
699 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
DR600InstrInfo.cpp549 R600::OpName::bank_swizzle); in fitsReadPortLimitations()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td116 bits<3> bank_swizzle;
123 let Word1{20-18} = bank_swizzle;
174 bits<3> bank_swizzle;
182 let Word1{20-18} = bank_swizzle;
DR600Packetizer.cpp303 R600::OpName::bank_swizzle); in addToPacket()
307 TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle); in addToPacket()
DEvergreenInstructions.td489 let bank_swizzle = 0;
534 BANK_SWIZZLE:$bank_swizzle),
556 BANK_SWIZZLE:$bank_swizzle),
588 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
DR600Instructions.td109 BANK_SWIZZLE:$bank_swizzle),
113 "$pred_sel $bank_swizzle"),
152 BANK_SWIZZLE:$bank_swizzle),
157 "$pred_sel $bank_swizzle"),
193 BANK_SWIZZLE:$bank_swizzle),
199 "$bank_swizzle"),
453 let bank_swizzle = 5;
457 let bank_swizzle = 5;
DR600InstrInfo.cpp549 R600::OpName::bank_swizzle); in fitsReadPortLimitations()
/external/mesa3d/src/gallium/drivers/r600/sfn/
Dsfn_instruction_alu.h116 int bank_swizzle() const {return m_bank_swizzle;} in bank_swizzle() function
Dsfn_ir_to_assembly.cpp326 if (ai.bank_swizzle() != alu_vec_unknown) in emit_alu()
327 alu.bank_swizzle_force = ai.bank_swizzle(); in emit_alu()

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