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Searched refs:fclass (Results 1 – 25 of 37) sorted by relevance

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/external/javassist/src/main/javassist/convert/
DTransformReadField.java45 static String isField(ClassPool pool, ConstPool cp, CtClass fclass, in isField() argument
52 if (c == fclass || (!is_private && isFieldInSuper(c, fclass, fname))) in isField()
59 static boolean isFieldInSuper(CtClass clazz, CtClass fclass, String fname) { in isFieldInSuper() argument
60 if (!clazz.subclassOf(fclass)) in isFieldInSuper()
65 return f.getDeclaringClass() == fclass; in isFieldInSuper()
/external/llvm/test/MC/Mips/msa/
Dtest_2rf.s3 # CHECK: fclass.w $w26, $w12 # encoding: [0x7b,0x20,0x66,0x9e]
4 # CHECK: fclass.d $w24, $w17 # encoding: [0x7b,0x21,0x8e,0x1e]
36 fclass.w $w26, $w12
37 fclass.d $w24, $w17
/external/llvm-project/llvm/test/MC/Mips/msa/
Dtest_2rf.s3 # CHECK: fclass.w $w26, $w12 # encoding: [0x7b,0x20,0x66,0x9e]
4 # CHECK: fclass.d $w24, $w17 # encoding: [0x7b,0x21,0x8e,0x1e]
36 fclass.w $w26, $w12
37 fclass.d $w24, $w17
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
D2rf_int_float.ll3 ; as fclass are also here.
14 %1 = tail call <4 x i32> @llvm.mips.fclass.w(<4 x float> %0)
19 declare <4 x i32> @llvm.mips.fclass.w(<4 x float>) nounwind
24 ; CHECK-DAG: fclass.w [[WD:\$w[0-9]+]], [[WS]]
35 %1 = tail call <2 x i64> @llvm.mips.fclass.d(<2 x double> %0)
40 declare <2 x i64> @llvm.mips.fclass.d(<2 x double>) nounwind
45 ; CHECK-DAG: fclass.d [[WD:\$w[0-9]+]], [[WS]]
/external/llvm/test/CodeGen/Mips/msa/
D2rf_int_float.ll3 ; as fclass are also here.
14 %1 = tail call <4 x i32> @llvm.mips.fclass.w(<4 x float> %0)
19 declare <4 x i32> @llvm.mips.fclass.w(<4 x float>) nounwind
24 ; CHECK-DAG: fclass.w [[WD:\$w[0-9]+]], [[WS]]
35 %1 = tail call <2 x i64> @llvm.mips.fclass.d(<2 x double> %0)
40 declare <2 x i64> @llvm.mips.fclass.d(<2 x double>) nounwind
45 ; CHECK-DAG: fclass.d [[WD:\$w[0-9]+]], [[WS]]
/external/capstone/suite/MC/Mips/
Dtest_2rf.s.cs2 0x7b,0x20,0x66,0x9e = fclass.w $w26, $w12
3 0x7b,0x21,0x8e,0x1e = fclass.d $w24, $w17
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_2rf.txt3 0x7b 0x20 0x66 0x9e # CHECK: fclass.w $w26, $w12
4 0x7b 0x21 0x8e 0x1e # CHECK: fclass.d $w24, $w17
/external/llvm-project/llvm/test/MC/Disassembler/Mips/msa/
Dtest_2rf.txt3 0x7b 0x20 0x66 0x9e # CHECK: fclass.w $w26, $w12
4 0x7b 0x21 0x8e 0x1e # CHECK: fclass.d $w24, $w17
/external/llvm/test/MC/Mips/mips32r2/
Dinvalid-msa.s12 …fclass.d $w14,$w27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
13 …fclass.w $w19,$w28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
/external/llvm-project/llvm/test/MC/Mips/mips32r2/
Dinvalid-msa.s12 …fclass.d $w14,$w27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
13 …fclass.w $w19,$w28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
/external/llvm-project/llvm/test/MC/RISCV/
Drv32d-valid.s108 # CHECK-ASM-AND-OBJ: fclass.d a3, ft10
110 fclass.d a3, ft10
Drv32zfh-valid.s105 # CHECK-ASM-AND-OBJ: fclass.h a3, ft10
107 fclass.h a3, ft10
Drv32f-valid.s105 # CHECK-ASM-AND-OBJ: fclass.s a3, ft10
107 fclass.s a3, ft10
/external/elfutils/tests/
Dtestfile-riscv64-dis1.expect.bz21testfile-riscv64-dis1.o: elf64-elf_riscv 2 3Disassembly of section .text ...
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoZfh.td178 def FCLASS_H : FPUnaryOp_r<0b1110010, 0b001, GPR, FPR16, "fclass.h">,
DRISCVInstrInfoD.td142 def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d">,
DRISCVInstrInfoF.td183 def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoD.td135 def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d">,
DRISCVInstrInfoF.td179 def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsScheduleP5600.td402 // fclass.[wd], fmax.[wd], fmax_a.[wd], fmin.[wd], fmin_a.[wd], flog2.[wd]
DMipsScheduleGeneric.td1521 // fclass.[wd], fmax.[wd], fmax_a.[wd], fmin.[wd], fmin_a.[wd], flog2.[wd]
/external/llvm-project/llvm/lib/Target/Mips/
DMipsScheduleP5600.td403 // fclass.[wd], fmax.[wd], fmax_a.[wd], fmin.[wd], fmin_a.[wd], flog2.[wd]
DMipsScheduleGeneric.td1524 // fclass.[wd], fmax.[wd], fmax_a.[wd], fmin.[wd], fmin_a.[wd], flog2.[wd]
/external/selinux/python/sepolicy/sepolicy/
Dgui.py1890 def init_modified_files_liststore(self, tree, app, ipage, operation, path, fclass, ftype): argument
1894 tree.set_value(iter, 2, fclass)
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td1976 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
1978 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,

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