Searched refs:getSubRegClass (Results 1 – 15 of 15) sorted by relevance
/external/llvm/lib/Target/AMDGPU/ |
D | SIRegisterInfo.h | 132 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
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D | SIFixSGPRCopies.cpp | 224 SrcRC = TRI->getSubRegClass(SrcRC, SrcSubReg); in foldVGPRCopyIntoRegSequence()
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D | SIInstrInfo.cpp | 1977 RC = TRI->getSubRegClass(RC, MO.getSubReg()); in isLegalRegOperand() 2713 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp() 2720 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp() 2767 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp() 2772 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp() 2781 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp() 2835 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
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D | SIRegisterInfo.cpp | 767 const TargetRegisterClass *SIRegisterInfo::getSubRegClass( in getSubRegClass() function in SIRegisterInfo
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIRegisterInfo.h | 178 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
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D | SIFixSGPRCopies.cpp | 296 SrcRC = TRI->getSubRegClass(SrcRC, SrcSubReg); in foldVGPRCopyIntoRegSequence()
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D | SIInstrInfo.cpp | 5312 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp() 5319 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp() 5373 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitAddSub() 5374 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitAddSub() 5439 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp() 5444 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp() 5457 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp() 5546 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
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D | SIRegisterInfo.cpp | 1393 const TargetRegisterClass *SIRegisterInfo::getSubRegClass( in getSubRegClass() function in SIRegisterInfo
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | SIRegisterInfo.h | 198 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
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D | GCNRegBankReassign.cpp | 311 const TargetRegisterClass *SubRC = TRI->getSubRegClass(RC, SubReg); in getPhysRegBank()
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D | SIFixSGPRCopies.cpp | 294 SrcRC = TRI->getSubRegClass(SrcRC, SrcSubReg); in foldVGPRCopyIntoRegSequence()
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D | SIInstrInfo.cpp | 6044 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp() 6051 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp() 6105 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitAddSub() 6106 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitAddSub() 6171 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp() 6176 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp() 6189 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp() 6278 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
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D | SIWholeQuadMode.cpp | 947 regClass = TRI->getSubRegClass(regClass, SubReg); in lowerCopyInstrs()
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D | SIRegisterInfo.cpp | 1847 const TargetRegisterClass *SIRegisterInfo::getSubRegClass( in getSubRegClass() function in SIRegisterInfo
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D | SIISelLowering.cpp | 3945 TRI->getSubRegClass(Src0RC, AMDGPU::sub0); in EmitInstrWithCustomInserter() 3947 TRI->getSubRegClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter() 4030 TRI->getSubRegClass(Src2RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()
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