| /external/llvm/lib/Target/X86/ |
| D | X86FixupBWInsts.cpp | 190 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead()
254 if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) != in tryReplaceCopy()
255 TRI->getSubRegIndex(NewDestReg, OldDest.getReg())) in tryReplaceCopy()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FixupBWInsts.cpp | 194 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead()
323 if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) != in tryReplaceCopy()
324 TRI->getSubRegIndex(NewDestReg, OldDest.getReg())) in tryReplaceCopy()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FixupBWInsts.cpp | 195 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead()
324 if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) != in tryReplaceCopy()
325 TRI->getSubRegIndex(NewDestReg, OldDest.getReg())) in tryReplaceCopy()
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 107 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg); in AddMachineRegPiece()
138 unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR); in AddMachineRegPiece()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | RDFRegisters.cpp | 182 LaneBitmask SM = TRI.getSubRegIndexLaneMask(SI.getSubRegIndex()); in aliasRM()
228 if (unsigned Idx = TRI.getSubRegIndex(R, RR.Reg)) in mapTo()
230 if (unsigned Idx = TRI.getSubRegIndex(RR.Reg, R)) { in mapTo()
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| D | HexagonBlockRanges.cpp | 245 unsigned SI = S.getSubRegIndex(); in getLiveIns()
285 SRs.insert({R.Reg, I.getSubRegIndex()}); in expandToSubRegs()
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| D | RDFCopy.cpp | 127 if (RR.Mask == TRI.getSubRegIndexLaneMask(S.getSubRegIndex())) in run()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | RDFRegisters.cpp | 187 LaneBitmask SM = TRI.getSubRegIndexLaneMask(SI.getSubRegIndex()); in aliasRM()
233 if (unsigned Idx = TRI.getSubRegIndex(R, RR.Reg)) in mapTo()
235 if (unsigned Idx = TRI.getSubRegIndex(RR.Reg, R)) { in mapTo()
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| /external/llvm/lib/CodeGen/ |
| D | MachineCopyPropagation.cpp | 139 unsigned SubIdx = TRI->getSubRegIndex(PreviousSrc, Src); in isNopCopy()
140 return SubIdx == TRI->getSubRegIndex(PreviousDef, Def); in isNopCopy()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCQPXLoadSplat.cpp | 109 TRI->getSubRegIndex(SrcReg, MI->getOperand(0).getReg()); in runOnMachineFunction()
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex() function in MCRegisterInfo
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCQPXLoadSplat.cpp | 104 TRI->getSubRegIndex(SrcReg, MI->getOperand(0).getReg()); in runOnMachineFunction()
|
| /external/llvm-project/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 44 unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg, in getSubRegIndex() function in MCRegisterInfo
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 44 unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg, in getSubRegIndex() function in MCRegisterInfo
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 353 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
497 unsigned getSubRegIndex() const { in getSubRegIndex() function
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/MIRParser/ |
| D | MIParser.h | 113 unsigned getSubRegIndex(StringRef Name);
|
| /external/llvm-project/llvm/include/llvm/CodeGen/MIRParser/ |
| D | MIParser.h | 114 unsigned getSubRegIndex(StringRef Name);
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 122 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg); in addMachineReg()
145 unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR); in addMachineReg()
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| /external/llvm-project/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 464 unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const;
618 unsigned getSubRegIndex() const { in getSubRegIndex() function
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 464 unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const;
618 unsigned getSubRegIndex() const { in getSubRegIndex() function
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| /external/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 123 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg); in addMachineReg()
146 unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR); in addMachineReg()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonBlockRanges.cpp | 245 unsigned SI = S.getSubRegIndex(); in getLiveIns()
285 SRs.insert({R.Reg, I.getSubRegIndex()}); in expandToSubRegs()
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| D | RDFCopy.cpp | 127 if (RR.Mask == TRI.getSubRegIndexLaneMask(S.getSubRegIndex())) in run()
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 400 Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j])); in computeSubRegs()
485 if (Cand == this || getSubRegIndex(Cand)) in computeSecondarySubRegs()
496 assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct"); in computeSecondarySubRegs()
498 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { in computeSecondarySubRegs()
537 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs()
1418 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3); in computeComposites()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | LivePhysRegs.cpp | 164 unsigned SI = S.getSubRegIndex(); in addBlockLiveIns()
|