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Searched refs:getValueAsListOfDefs (Results 1 – 25 of 62) sorted by relevance

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/external/llvm-project/libc/utils/LibcTableGenUtil/
DAPIIndexer.cpp83 auto HeaderSpecList = StandardSpec->getValueAsListOfDefs("Headers"); in indexStandardSpecDef()
88 auto MacroSpecList = HeaderSpec->getValueAsListOfDefs("Macros"); in indexStandardSpecDef()
94 auto TypeSpecList = HeaderSpec->getValueAsListOfDefs("Types"); in indexStandardSpecDef()
98 auto FunctionSpecList = HeaderSpec->getValueAsListOfDefs("Functions"); in indexStandardSpecDef()
106 HeaderSpec->getValueAsListOfDefs("Enumerations"); in indexStandardSpecDef()
119 auto MacroDefList = PublicAPI->getValueAsListOfDefs("Macros"); in indexPublicAPIDef()
123 auto TypeDeclList = PublicAPI->getValueAsListOfDefs("TypeDeclarations"); in indexPublicAPIDef()
/external/llvm-project/llvm/include/llvm/TableGen/
DDirectiveEmitter.h109 return Def->getValueAsListOfDefs("allowedClauses"); in getAllowedClauses()
113 return Def->getValueAsListOfDefs("allowedOnceClauses"); in getAllowedOnceClauses()
117 return Def->getValueAsListOfDefs("allowedExclusiveClauses"); in getAllowedExclusiveClauses()
121 return Def->getValueAsListOfDefs("requiredClauses"); in getRequiredClauses()
174 return Def->getValueAsListOfDefs("allowedClauseValues"); in getClauseVals()
/external/llvm-project/mlir/tools/mlir-tblgen/
DLLVMIRIntrinsicGen.cpp53 auto results = record.getValueAsListOfDefs(listName); in getOverloadableTypeIdxs()
118 auto operands = record.getValueAsListOfDefs(fieldOperands); in getNumOperands()
131 auto results = record.getValueAsListOfDefs(fieldResults); in getNumResults()
143 auto props = record.getValueAsListOfDefs(fieldTraits); in hasSideEffects()
154 auto props = record.getValueAsListOfDefs(fieldTraits); in isCommutative()
/external/llvm-project/clang/utils/TableGen/
DClangOpcodesEmitter.cpp74 for (auto *Type : TypeClass->getDef()->getValueAsListOfDefs("Types")) { in Enumerate()
119 auto Args = R->getValueAsListOfDefs("Args"); in EmitInterp()
164 for (auto *Arg : R->getValueAsListOfDefs("Args")) in EmitDisasm()
179 auto Args = R->getValueAsListOfDefs("Args"); in EmitEmitter()
205 auto Args = R->getValueAsListOfDefs("Args"); in EmitProto()
239 auto Args = R->getValueAsListOfDefs("Args"); in EmitGroup()
294 auto Cases = TypeClass->getDef()->getValueAsListOfDefs("Types"); in EmitGroup()
322 auto Args = R->getValueAsListOfDefs("Args"); in EmitEval()
DClangSACheckersEmitter.cpp233 ->getValueAsListOfDefs("PackageOptions"); in EmitClangSACheckers()
273 Checker->getValueAsListOfDefs("Dependencies")) { in EmitClangSACheckers()
298 Checker->getValueAsListOfDefs("WeakDependencies")) { in EmitClangSACheckers()
333 ->getValueAsListOfDefs("CheckerOptions"); in EmitClangSACheckers()
DClangOpenCLBuiltinEmitter.cpp381 T->getValueAsDef("TypeList")->getValueAsListOfDefs("List").size(); in VerifySignature()
413 auto Signature = B->getValueAsListOfDefs("Signature"); in GetOverloads()
509 << Overload.first->getValueAsListOfDefs("Signature").size() << ", " in EmitBuiltinTable()
715 GenType->getValueAsDef("TypeList")->getValueAsListOfDefs("List")) { in EmitQualTypeFinder()
724 << GenType->getValueAsDef("TypeList")->getValueAsListOfDefs("List") in EmitQualTypeFinder()
DClangAttrEmitter.cpp76 std::vector<Record *> Spellings = Attr.getValueAsListOfDefs("Spellings"); in GetFlattenedSpellings()
1593 std::vector<Record*> Accessors = R.getValueAsListOfDefs("Accessors"); in writeAttrAccessorDefinition()
1743 ->getValueAsListOfDefs("Subjects"); in getSubjects()
1750 std::vector<Record *> Opts = Constraint->getValueAsListOfDefs("LangOpts"); in getLangOpts()
1754 return MetaSubject->getValueAsListOfDefs("LangOpts"); in getLangOpts()
1869 SubjectContainer->getValueAsListOfDefs("Subjects"); in PragmaClangAttributeSupport()
1886 MetaSubject->getValueAsListOfDefs("Constraints"); in PragmaClangAttributeSupport()
1971 std::vector<Record *> Subjects = SubjectObj->getValueAsListOfDefs("Subjects"); in isAttributedSupported()
2022 std::vector<Record *> Subjects = SubjectObj->getValueAsListOfDefs("Subjects"); in generateStrictConformsTo()
2147 std::vector<Record *> Args = Attr->getValueAsListOfDefs("Args"); in emitClangAttrTypeArgList()
[all …]
/external/llvm-project/llvm/utils/TableGen/
DExegesisEmitter.cpp78 Def->getValueAsListOfDefs("IssueCounters")) { in collectPfmCounters()
115 Def.getValueAsListOfDefs("IssueCounters").size(); in emitPfmCountersInfo()
159 return !Def->getValueAsListOfDefs("IssueCounters").empty(); in emitPfmCounters()
165 for (const Record *ICDef : Def->getValueAsListOfDefs("IssueCounters")) in emitPfmCounters()
DCodeGenSchedule.cpp258 RecVec Opcodes = R->getValueAsListOfDefs("Opcodes"); in checkSTIPredicates()
299 RecVec Classes = Def->getValueAsListOfDefs("Classes"); in processSTIPredicate()
305 RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes"); in processSTIPredicate()
330 RecVec Classes = Def->getValueAsListOfDefs("Classes"); in processSTIPredicate()
337 RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes"); in processSTIPredicate()
553 if (!ModelKey->getValueAsListOfDefs("IID").empty()) in addProcModel()
569 RecVec Seq = RWDef->getValueAsListOfDefs("Writes"); in scanSchedRW()
575 RecVec Vars = RWDef->getValueAsListOfDefs("Variants"); in scanSchedRW()
578 RecVec Selected = Variant->getValueAsListOfDefs("Selected"); in scanSchedRW()
600 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW"); in collectSchedRW()
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DDFAPacketizerEmitter.cpp112 std::vector<Record *> FUs = Proc->getValueAsListOfDefs("FU"); in collectAllFuncUnits()
142 std::vector<Record *> FUs = Func->getValueAsListOfDefs("CFD"); in collectAllComboFuncs()
154 FuncData->getValueAsListOfDefs("FuncList"); in collectAllComboFuncs()
181 for (Record *StageDef : Itinerary->getValueAsListOfDefs("Stages")) { in getResourcesForItinerary()
183 for (Record *Unit : StageDef->getValueAsListOfDefs("Units")) { in getResourcesForItinerary()
DPredicateExpander.cpp242 const RecVec &Opcodes = Rec->getValueAsListOfDefs("Opcodes"); in expandOpcodeSwitchCase()
286 expandOpcodeSwitchStatement(OS, Rec->getValueAsListOfDefs("Cases"), in expandStatement()
360 return expandCheckPseudo(OS, Rec->getValueAsListOfDefs("ValidOpcodes")); in expandPredicate()
363 return expandCheckOpcode(OS, Rec->getValueAsListOfDefs("ValidOpcodes")); in expandPredicate()
366 return expandPredicateSequence(OS, Rec->getValueAsListOfDefs("Predicates"), in expandPredicate()
370 return expandPredicateSequence(OS, Rec->getValueAsListOfDefs("Predicates"), in expandPredicate()
424 RecVec Delegates = Fn.getDeclaration()->getValueAsListOfDefs("Delegates"); in expandPrologue()
DSubtargetEmitter.cpp234 RecVec ImpliesList = Feature->getValueAsListOfDefs("Implies"); in FeatureKeyValues()
268 RecVec FeatureList = Processor->getValueAsListOfDefs("Features"); in CPUKeyValues()
269 RecVec TuneFeatureList = Processor->getValueAsListOfDefs("TuneFeatures"); in CPUKeyValues()
301 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
314 RecVec UnitList = Stage->getValueAsListOfDefs("Units"); in FormItineraryStageString()
361 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
392 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
406 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
632 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResourceSubUnits()
796 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResources()
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DCodeGenHwModes.cpp32 std::vector<Record*> Modes = R->getValueAsListOfDefs("Modes"); in HwModeSelect()
33 std::vector<Record*> Objects = R->getValueAsListOfDefs("Objects"); in HwModeSelect()
DSDNodeProperties.cpp17 for (Record *Property : R->getValueAsListOfDefs("Properties")) { in parseSDPatternOperatorProperties()
DCodeGenTarget.cpp299 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); in getAsmParser()
311 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); in getAsmParserVariant()
323 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); in getAsmParserVariantCount()
330 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); in getAsmWriter()
571 RootNodes = R->getValueAsListOfDefs("RootNodes"); in ComplexPattern()
586 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); in ComplexPattern()
DInstrInfoEmitter.cpp538 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); in run()
543 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); in run()
804 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); in emitRecord()
810 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); in emitRecord()
/external/llvm/utils/TableGen/
DCodeGenSchedule.cpp170 if (!ModelKey->getValueAsListOfDefs("IID").empty()) in addProcModel()
186 RecVec Seq = RWDef->getValueAsListOfDefs("Writes"); in scanSchedRW()
192 RecVec Vars = RWDef->getValueAsListOfDefs("Variants"); in scanSchedRW()
195 RecVec Selected = (*VI)->getValueAsListOfDefs("Selected"); in scanSchedRW()
217 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW"); in collectSchedRW()
231 RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites"); in collectSchedRW()
246 RecVec RWDefs = (*II)->getValueAsListOfDefs("OperandReadWrites"); in collectSchedRW()
293 findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence, in collectSchedRW()
358 RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites"); in hasReadOfWrite()
511 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); in collectSchedClasses()
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DSubtargetEmitter.cpp193 Feature->getValueAsListOfDefs("Implies"); in FeatureKeyValues()
239 Processor->getValueAsListOfDefs("Features"); in CPUKeyValues()
279 ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
292 const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units"); in FormItineraryStageString()
340 ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
372 std::vector<Record*> FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
386 std::vector<Record*> BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
617 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResources()
762 SubResources = PRDef->getValueAsListOfDefs("Resources"); in ExpandProcResources()
783 RecVec SuperResources = PR->getValueAsListOfDefs("Resources"); in ExpandProcResources()
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DCodeGenTarget.cpp183 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); in getAsmParser()
195 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); in getAsmParserVariant()
207 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); in getAsmParserVariantCount()
214 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); in getAsmWriter()
394 RootNodes = R->getValueAsListOfDefs("RootNodes"); in ComplexPattern()
398 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); in ComplexPattern()
DDFAPacketizerEmitter.cpp656 std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU"); in collectAllFuncUnits()
698 std::vector<Record*> FUs = Func->getValueAsListOfDefs("CFD"); in collectAllComboFuncs()
711 FuncData->getValueAsListOfDefs("FuncList"); in collectAllComboFuncs()
743 ItinData->getValueAsListOfDefs("Stages"); in collectOneInsnClass()
759 Stage->getValueAsListOfDefs("Units"); in collectOneInsnClass()
878 std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID"); in run()
DInstrInfoEmitter.cpp361 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); in run()
366 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); in run()
527 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); in emitRecord()
533 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); in emitRecord()
/external/llvm-project/mlir/lib/TableGen/
DPass.cpp68 for (auto *init : def->getValueAsListOfDefs("options")) in Pass()
70 for (auto *init : def->getValueAsListOfDefs("statistics")) in Pass()
/external/clang/utils/TableGen/
DClangAttrEmitter.cpp74 std::vector<Record *> Spellings = Attr.getValueAsListOfDefs("Spellings"); in GetFlattenedSpellings()
1410 std::vector<Record*> Accessors = R.getValueAsListOfDefs("Accessors"); in writeAttrAccessorDefinition()
1531 std::vector<Record *> Args = Attr->getValueAsListOfDefs("Args"); in emitClangAttrTypeArgList()
1587 std::vector<Record *> Args = Attr->getValueAsListOfDefs("Args"); in emitClangAttrIdentifierArgList()
1625 (void)R.getValueAsListOfDefs("Documentation"); in EmitClangAttrClass()
1641 std::vector<Record*> ArgRecords = R.getValueAsListOfDefs("Args"); in EmitClangAttrClass()
1819 std::vector<Record*> ArgRecords = R.getValueAsListOfDefs("Args"); in EmitClangAttrImpl()
2131 ArgRecords = R.getValueAsListOfDefs("Args"); in EmitClangAttrPCHRead()
2165 Args = R.getValueAsListOfDefs("Args"); in EmitClangAttrPCHWrite()
2254 std::vector<Record *> Spellings = Attr->getValueAsListOfDefs("Spellings"); in GenerateHasAttrSpellingStringSwitch()
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/external/llvm-project/libc/utils/HdrGen/PrototypeTestGen/
DPrototypeTestGen.cpp48 auto args = functionSpec->getValueAsListOfDefs("Args"); in TestGeneratorMain()
/external/capstone/contrib/sysz_update/
D0006-capstone-generate-MappingInsn.inc.patch105 + for (Record *Use : Inst->TheDef->getValueAsListOfDefs("Uses")) {
109 + for (Record *Def : Inst->TheDef->getValueAsListOfDefs("Defs")) {

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