Searched refs:ipsr (Results 1 – 15 of 15) sorted by relevance
| /external/pigweed/pw_interrupt_cortex_m/public/pw_interrupt_cortex_m/ |
| D | context_inline.h | 27 uint32_t ipsr; in InInterruptContext() local
28 asm volatile("MRS %0, ipsr" : "=r"(ipsr)); in InInterruptContext()
29 return ipsr != 0; in InInterruptContext()
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| /external/llvm/test/MC/ARM/ |
| D | thumb2-mclass.s | 17 mrs r0, ipsr
29 @ CHECK: mrs r0, ipsr @ encoding: [0xef,0xf3,0x05,0x80]
49 msr ipsr, r0
73 @ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88]
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| /external/llvm-project/llvm/test/MC/ARM/ |
| D | thumb2-mclass.s | 17 mrs r0, ipsr
29 @ CHECK: mrs r0, ipsr @ encoding: [0xef,0xf3,0x05,0x80]
49 msr ipsr, r0
73 @ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88]
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| /external/capstone/suite/MC/ARM/ |
| D | thumb2-mclass.s.cs | 6 0xef,0xf3,0x05,0x80 = mrs r0, ipsr
32 0x80,0xf3,0x05,0x88 = msr ipsr, r0
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| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-MSR-MClass.txt | 11 # CHECK: mrs r0, ipsr
74 # CHECK: msr ipsr, r0
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-MSR-MClass.txt | 11 # CHECK: mrs r0, ipsr
74 # CHECK: msr ipsr, r0
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| /external/llvm/test/CodeGen/ARM/ |
| D | special-reg-mcore.ll | 15 ; MCORE: mrs r1, ipsr
75 ; MCORE: msr ipsr, r0
134 !16 = !{!"ipsr"}
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| D | special-reg-v8m-base.ll | 13 ; CHECK: mrs r1, ipsr
77 ; CHECK: msr ipsr, r0
128 !16 = !{!"ipsr"}
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| D | special-reg-v8m-main.ll | 13 ; MAINLINE: mrs r1, ipsr
109 ; MAINLINE: msr ipsr, r0
192 !16 = !{!"ipsr"}
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| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | special-reg-v8m-base.ll | 13 ; CHECK: mrs r1, ipsr
77 ; CHECK: msr ipsr, r0
128 !16 = !{!"ipsr"}
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| D | special-reg-mcore.ll | 15 ; MCORE: mrs r1, ipsr @ encoding: [0xef,0xf3,0x05,0x81]
75 ; MCORE: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88]
134 !16 = !{!"ipsr"}
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| D | special-reg-v8m-main.ll | 13 ; MAINLINE: mrs r1, ipsr
106 ; MAINLINE: msr ipsr, r0
187 !16 = !{!"ipsr"}
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenSystemRegister.inc | 57 ipsr = 2053,
270 { "ipsr", 0x805, 0x105, 0x805, {} }, // 16
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMSystemRegister.td | 66 def : MClassSysReg<0, 0, 1, 0x805, "ipsr">;
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMSystemRegister.td | 66 def : MClassSysReg<0, 0, 1, 0x805, "ipsr">;
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