| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.h | 148 bool is64BitVector() const { in is64BitVector() function
149 return isSimple() ? V.is64BitVector() : isExtended64BitVector(); in is64BitVector()
|
| D | MachineValueType.h | 240 bool is64BitVector() const { in is64BitVector() function
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.h | 177 bool is64BitVector() const { in is64BitVector() function
178 return isSimple() ? V.is64BitVector() : isExtended64BitVector(); in is64BitVector()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 310 bool is64BitVector);
1868 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1870 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2024 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
2025 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVLD()
2052 if (!is64BitVector) in SelectVLD()
2068 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
2069 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
2137 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
2166 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
[all …]
|
| D | ARMISelLowering.cpp | 6012 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTPOP()
6018 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP()
6892 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
6928 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
6966 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
6999 if (VT.is64BitVector() && EltSz == 32) in isVZIP_v_undef_Mask()
7623 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
8620 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
8621 Op1.getValueType().is64BitVector() && in LowerMUL()
11113 if (!N->getValueType(0).is64BitVector()) in AddCombineToVPADD()
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 269 bool is64BitVector);
1688 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1690 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1822 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
1823 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVLD()
1850 if (!is64BitVector) in SelectVLD()
1866 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
1867 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
1934 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
1962 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
[all …]
|
| D | ARMISelLowering.cpp | 4656 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTTZ()
4661 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16; in LowerCTTZ()
4668 EVT VT32Bit = VT.is64BitVector() ? MVT::v2i32 : MVT::v4i32; in LowerCTTZ()
4706 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in getCTPOP16BitCounts()
4729 if (VT.is64BitVector()) { in lowerCTPOP16BitElements()
4763 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16; in lowerCTPOP32BitElements()
4771 if (VT.is64BitVector()) { in lowerCTPOP32BitElements()
5473 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
5509 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
5547 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
[all …]
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.h | 172 bool is64BitVector() const { in is64BitVector() function
173 return isSimple() ? V.is64BitVector() : isExtended64BitVector(); in is64BitVector()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 330 bool is64BitVector);
1915 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1917 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2072 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
2073 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVLD()
2102 if (!is64BitVector) in SelectVLD()
2118 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
2119 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
2187 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
2217 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
[all …]
|
| D | ARMISelLowering.cpp | 6205 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTPOP()
6211 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP()
7093 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
7129 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
7167 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
7200 if (VT.is64BitVector() && EltSz == 32) in isVZIP_v_undef_Mask()
7929 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
8926 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
8927 Op1.getValueType().is64BitVector() && in LowerMUL()
11560 if (!N->getValueType(0).is64BitVector()) in AddCombineToVPADD()
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.h | 96 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
|
| D | AArch64ISelLowering.cpp | 2262 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
2263 Op1.getValueType().is64BitVector() && in LowerMUL()
2517 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
6545 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
8207 if (!NarrowTy.is64BitVector()) in tryExtendDUPToExtractHigh()
8424 assert(LHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
8425 RHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
|
| D | AArch64FastISel.cpp | 2865 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2909 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
|
| D | AArch64ISelDAGToDAG.cpp | 1100 } else if (VT == MVT::f64 || VT.is64BitVector()) { in tryIndexedLoad()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.cpp | 97 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
|
| D | AArch64ISelLowering.cpp | 2924 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
2925 Op1.getValueType().is64BitVector() && in LowerMUL()
3411 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
5194 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTPOP()
5200 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP()
8249 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
10511 if (!NarrowTy.is64BitVector()) in tryExtendDUPToExtractHigh()
10729 assert(LHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
10730 RHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
|
| D | AArch64FastISel.cpp | 2996 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
3040 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
|
| D | AArch64ISelDAGToDAG.cpp | 1245 } else if (VT == MVT::f64 || VT.is64BitVector()) { in tryIndexedLoad()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.cpp | 144 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
|
| D | AArch64ISelLowering.cpp | 3490 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
3491 Op1.getValueType().is64BitVector() && in LowerMUL()
4370 if (OverrideNEON && (VT.is128BitVector() || VT.is64BitVector())) in useSVEForFixedLengthVectorVT()
4513 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
6440 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTPOP()
6446 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP()
7964 if (!SrcVT.is64BitVector()) { in ReconstructShuffle()
9865 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
12204 if (!(VT.is64BitVector() || VT.is128BitVector())) in performANDCombine()
12617 if (!NarrowTy.is64BitVector()) in tryExtendDUPToExtractHigh()
[all …]
|
| D | AArch64FastISel.cpp | 2994 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
3038 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
|
| D | AArch64ISelDAGToDAG.cpp | 1327 } else if (VT == MVT::f64 || VT.is64BitVector()) { in tryIndexedLoad()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 341 bool is64BitVector() const { in is64BitVector() function
|
| /external/llvm-project/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 371 bool is64BitVector() const { in is64BitVector() function
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 42818 N0.getOperand(0).getValueType().is64BitVector() && in combineVectorPack()
42823 N1.getOperand(0).getValueType().is64BitVector() && in combineVectorPack()
|