| /external/arm-trusted-firmware/drivers/rpi3/sdhost/ |
| D | rpi3_sdhost.c | 50 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_sdhost_waitcommand() local
54 while ((mmio_read_32(reg_base + HC_COMMAND) & HC_CMD_ENABLE) in rpi3_sdhost_waitcommand()
73 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in send_command_raw() local
79 status = mmio_read_32(reg_base + HC_HOSTSTATUS); in send_command_raw()
81 mmio_write_32(reg_base + HC_HOSTSTATUS, status); in send_command_raw()
87 mmio_write_32(reg_base + HC_ARGUMENT, arg); in send_command_raw()
88 mmio_write_32(reg_base + HC_COMMAND, cmd | HC_CMD_ENABLE); in send_command_raw()
137 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_drain_fifo() local
142 while (mmio_read_32(reg_base + HC_HOSTSTATUS) & HC_HSTST_HAVEDATA) { in rpi3_drain_fifo()
143 mmio_read_32(reg_base + HC_DATAPORT); in rpi3_drain_fifo()
[all …]
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| /external/arm-trusted-firmware/drivers/imx/usdhc/ |
| D | imx_usdhc.c | 44 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_set_clk() local
58 mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN); in imx_usdhc_set_clk()
59 mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk); in imx_usdhc_set_clk()
62 mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_PER_CLKEN | VENDSPEC_CARD_CLKEN); in imx_usdhc_set_clk()
68 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_initialize() local
70 assert((imx_usdhc_params.reg_base & MMC_BLOCK_MASK) == 0); in imx_usdhc_initialize()
73 mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTA); in imx_usdhc_initialize()
76 while ((mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTA)) { in imx_usdhc_initialize()
82 mmio_write_32(reg_base + MMCBOOT, 0); in imx_usdhc_initialize()
83 mmio_write_32(reg_base + MIXCTRL, 0); in imx_usdhc_initialize()
[all …]
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| /external/arm-trusted-firmware/drivers/synopsys/emmc/ |
| D | dw_mmc.c | 145 mmio_write_32(dw_params.reg_base + DWMMC_CMD, in dw_update_clk()
149 data = mmio_read_32(dw_params.reg_base + DWMMC_CMD); in dw_update_clk()
152 data = mmio_read_32(dw_params.reg_base + DWMMC_RINTSTS); in dw_update_clk()
173 data = mmio_read_32(dw_params.reg_base + DWMMC_STATUS); in dw_set_clk()
177 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 0); in dw_set_clk()
180 mmio_write_32(dw_params.reg_base + DWMMC_CLKDIV, div); in dw_set_clk()
184 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 1); in dw_set_clk()
185 mmio_write_32(dw_params.reg_base + DWMMC_CLKSRC, 0); in dw_set_clk()
194 assert((dw_params.reg_base & MMC_BLOCK_MASK) == 0); in dw_init()
196 base = dw_params.reg_base; in dw_init()
[all …]
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| /external/arm-trusted-firmware/plat/socionext/uniphier/ |
| D | uniphier_nand.c | 52 uintptr_t reg_base; member
88 mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 0); in uniphier_nand_block_isbad()
90 mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1); in uniphier_nand_block_isbad()
103 status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0); in uniphier_nand_block_isbad()
125 mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 1); in uniphier_nand_read_pages()
126 mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 1); in uniphier_nand_read_pages()
128 mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1); in uniphier_nand_read_pages()
148 status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0); in uniphier_nand_read_pages()
151 mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 0); in uniphier_nand_read_pages()
241 nand->reg_base = nand->host_base + 0x100000; in uniphier_nand_hw_init()
[all …]
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| /external/arm-trusted-firmware/drivers/rpi3/gpio/ |
| D | rpi3_gpio.c | 14 static uintptr_t reg_base; variable
48 uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN); in rpi3_gpio_get_select()
73 uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN); in rpi3_gpio_set_select()
109 uintptr_t reg_lev = reg_base + RPI3_GPIO_GPLEV(regN); in rpi3_gpio_get_value()
121 uintptr_t reg_set = reg_base + RPI3_GPIO_GPSET(regN); in rpi3_gpio_set_value()
122 uintptr_t reg_clr = reg_base + RPI3_GPIO_GPSET(regN); in rpi3_gpio_set_value()
138 uintptr_t reg_pud = reg_base + RPI3_GPIO_GPPUD; in rpi3_gpio_set_pull()
139 uintptr_t reg_clk = reg_base + RPI3_GPIO_GPPUDCLK(regN); in rpi3_gpio_set_pull()
161 reg_base = RPI3_GPIO_BASE; in rpi3_gpio_init()
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| /external/arm-trusted-firmware/drivers/marvell/comphy/ |
| D | phy-comphy-3700.c | 610 uintptr_t reg_base = 0; in mvebu_a3700_comphy_usb3_power_on() local
625 reg_base = COMPHY_INDIRECT_REG; in mvebu_a3700_comphy_usb3_power_on()
629 reg_base = USB3_GBE1_PHY; in mvebu_a3700_comphy_usb3_power_on()
642 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK, in mvebu_a3700_comphy_usb3_power_on()
655 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask, mode); in mvebu_a3700_comphy_usb3_power_on()
660 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR, in mvebu_a3700_comphy_usb3_power_on()
667 usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR, in mvebu_a3700_comphy_usb3_power_on()
674 usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0, in mvebu_a3700_comphy_usb3_power_on()
681 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2, in mvebu_a3700_comphy_usb3_power_on()
690 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3, in mvebu_a3700_comphy_usb3_power_on()
[all …]
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| /external/arm-trusted-firmware/drivers/ufs/ |
| D | ufs.c | 59 assert((ufs_params.reg_base != 0) && (val != NULL)); in ufshc_dme_get()
61 base = ufs_params.reg_base; in ufshc_dme_get()
94 assert((ufs_params.reg_base != 0)); in ufshc_dme_set()
96 base = ufs_params.reg_base; in ufshc_dme_set()
161 data = mmio_read_32(ufs_params.reg_base + UTRLDBR); in get_empty_slot()
221 mmio_write_32(ufs_params.reg_base + UTRLBA, in ufs_prepare_cmd()
223 mmio_write_32(ufs_params.reg_base + UTRLBAU, in ufs_prepare_cmd()
324 mmio_write_32(ufs_params.reg_base + UTRLBA, in ufs_prepare_query()
326 mmio_write_32(ufs_params.reg_base + UTRLBAU, in ufs_prepare_query()
377 mmio_write_32(ufs_params.reg_base + UTRLBA, in ufs_prepare_nop_out()
[all …]
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| /external/arm-trusted-firmware/plat/layerscape/common/ |
| D | ls_tzc380.c | 22 unsigned int reg_base; in tzc380_set_region() local
25 reg_base = (tzasc_base + TZASC_REGIONS_REG + (region_id << 4)); in tzc380_set_region()
28 reg = (reg_base + TZASC_REGION_ATTR_OFFSET); in tzc380_set_region()
31 reg = reg_base + TZASC_REGION_LOWADDR_OFFSET; in tzc380_set_region()
35 reg = reg_base + TZASC_REGION_HIGHADDR_OFFSET; in tzc380_set_region()
38 reg = reg_base + TZASC_REGION_ATTR_OFFSET; in tzc380_set_region()
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| /external/python/cpython2/Modules/_ctypes/libffi/src/avr32/ |
| D | ffi.c | 72 char *reg_base = stack; in ffi_prep_args() local
82 *(void**)reg_base = ecif->rvalue; in ffi_prep_args()
111 addr = reg_base + (index * 4); in ffi_prep_args()
118 addr = reg_base + 4; in ffi_prep_args()
123 addr = reg_base + 12; in ffi_prep_args()
166 printf("r%d: 0x%08x\n", 12 - i, ((unsigned int*)reg_base)[i]); in ffi_prep_args()
275 register char *reg_base = stack; in ffi_prep_incoming_args_SYSV() local
290 *rvalue = *(void **)reg_base; in ffi_prep_incoming_args_SYSV()
320 *p_argv = (void*)reg_base + (index * 4); in ffi_prep_incoming_args_SYSV()
327 *p_argv = (void*)reg_base + 4; in ffi_prep_incoming_args_SYSV()
[all …]
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| /external/libffi/src/avr32/ |
| D | ffi.c | 72 char *reg_base = stack; in ffi_prep_args() local
82 *(void**)reg_base = ecif->rvalue; in ffi_prep_args()
111 addr = reg_base + (index * 4); in ffi_prep_args()
118 addr = reg_base + 4; in ffi_prep_args()
123 addr = reg_base + 12; in ffi_prep_args()
166 printf("r%d: 0x%08x\n", 12 - i, ((unsigned int*)reg_base)[i]); in ffi_prep_args()
275 register char *reg_base = stack; in ffi_prep_incoming_args_SYSV() local
290 *rvalue = *(void **)reg_base; in ffi_prep_incoming_args_SYSV()
320 *p_argv = (void*)reg_base + (index * 4); in ffi_prep_incoming_args_SYSV()
327 *p_argv = (void*)reg_base + 4; in ffi_prep_incoming_args_SYSV()
[all …]
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| /external/arm-trusted-firmware/drivers/synopsys/ufs/ |
| D | dw_ufs.c | 23 assert((params != NULL) && (params->reg_base != 0)); in dwufs_phy_init()
25 base = params->reg_base; in dwufs_phy_init()
103 assert((params != NULL) && (params->reg_base != 0)); in dwufs_phy_set_pwr_mode()
105 base = params->reg_base; in dwufs_phy_set_pwr_mode()
196 ufs_params.reg_base = params->reg_base; in dw_ufs_init()
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| /external/igt-gpu-tools/tests/i915/ |
| D | gem_mocs_settings.c | 234 uint32_t reg_base) in create_read_batch() argument
240 batch[offset+1] = reg_base + (index * sizeof(uint32_t)); in create_read_batch()
260 uint32_t reg_base, in do_read_registers() argument
283 create_read_batch(reloc, batch, dst_handle, size, reg_base); in do_read_registers()
297 uint32_t reg_base) in create_write_batch() argument
305 batch[offset++] = reg_base + (i * 4); in create_write_batch()
316 uint32_t reg_base, in write_registers() argument
334 execbuf.batch_len = create_write_batch(batch, values, size, reg_base); in write_registers()
351 const uint32_t reg_base = get_engine_base(fd, engine); in check_control_registers() local
361 reg_base, in check_control_registers()
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| /external/arm-trusted-firmware/drivers/st/mmc/ |
| D | stm32_sdmmc2.c | 151 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_init()
187 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_send_cmd_req()
418 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_set_ios()
472 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_prepare()
538 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_read()
648 if (fdt32_to_cpu(*cuint) == sdmmc2_params.reg_base) { in stm32_sdmmc2_dt_get_config()
730 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && in stm32_sdmmc2_mmc_init()
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| /external/arm-trusted-firmware/drivers/imx/timer/ |
| D | imx_gpt.h | 12 void imx_gpt_ops_init(uintptr_t reg_base);
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| /external/arm-trusted-firmware/include/drivers/synopsys/ |
| D | dw_mmc.h | 13 uintptr_t reg_base; member
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| /external/arm-trusted-firmware/include/drivers/st/ |
| D | stm32_sdmmc2.h | 15 uintptr_t reg_base; member
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| /external/arm-trusted-firmware/plat/intel/soc/common/include/ |
| D | socfpga_private.h | 20 .reg_base = SOCFPGA_MMC_REG_BASE \
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| /external/arm-trusted-firmware/drivers/st/spi/ |
| D | stm32_qspi.c | 107 uintptr_t reg_base; member
118 return stm32_qspi.reg_base; in qspi_base()
473 &stm32_qspi.reg_base, &size); in stm32_qspi_init()
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| /external/arm-trusted-firmware/include/drivers/ |
| D | dw_ufs.h | 102 uintptr_t reg_base; member
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| /external/arm-trusted-firmware/plat/hisilicon/poplar/include/ |
| D | hi3798cv200.h | 75 .reg_base = REG_BASE_MCI, \
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| /external/arm-trusted-firmware/include/drivers/rpi3/sdhost/ |
| D | rpi3_sdhost.h | 16 uintptr_t reg_base; member
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| /external/arm-trusted-firmware/plat/rpi/rpi3/ |
| D | rpi3_bl2_setup.c | 35 params.reg_base = RPI3_SDHOST_BASE; in rpi3_sdhost_setup()
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| /external/arm-trusted-firmware/plat/imx/imx7/warp7/ |
| D | warp7_bl2_el3_setup.c | 105 params.reg_base = PLAT_WARP7_BOOT_MMC_BASE; in warp7_usdhc_setup()
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| /external/arm-trusted-firmware/plat/imx/imx7/picopi/ |
| D | picopi_bl2_el3_setup.c | 99 params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE; in picopi_usdhc_setup()
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| /external/arm-trusted-firmware/plat/hisilicon/hikey/ |
| D | hikey_bl1_setup.c | 96 params.reg_base = DWMMC0_BASE; in bl1_platform_setup()
|