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Searched refs:s_lshl_b64 (Results 1 – 25 of 37) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dshl.ll212 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
254 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 64, s{{[0-9]+}}
262 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 1, s{{[0-9]+}}
270 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{[0-9]+}}
278 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, s{{[0-9]+}}
286 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 0.5, s{{[0-9]+}}
294 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -0.5, s{{[0-9]+}}
302 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 2.0, s{{[0-9]+}}
310 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -2.0, s{{[0-9]+}}
318 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 4.0, s{{[0-9]+}}
[all …]
Drotl.i64.ll5 ; BOTH-DAG: s_lshl_b64
Drotr.i64.ll7 ; BOTH-DAG: s_lshl_b64
Dtrunc.ll36 ; SI: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2
Dsext-in-reg.ll79 ; SI: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
93 ; SI: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
107 ; SI: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
122 ; SI: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dshift-i128.ll193 ; GCN-NEXT: s_lshl_b64 s[0:1], s[6:7], s8
196 ; GCN-NEXT: s_lshl_b64 s[2:3], s[4:5], s2
209 ; GCN-NEXT: s_lshl_b64 s[0:1], s[4:5], s8
231 ; GCN-NEXT: s_lshl_b64 s[10:11], s[6:7], s9
271 ; GCN-NEXT: s_lshl_b64 s[0:1], s[6:7], s0
460 ; GCN-NEXT: s_lshl_b64 s[24:25], s[10:11], s16
463 ; GCN-NEXT: s_lshl_b64 s[4:5], s[8:9], s4
481 ; GCN-NEXT: s_lshl_b64 s[10:11], s[14:15], s20
482 ; GCN-NEXT: s_lshl_b64 s[4:5], s[12:13], s4
497 ; GCN-NEXT: s_lshl_b64 s[2:3], s[8:9], s16
[all …]
Drotl.i64.ll5 ; BOTH-DAG: s_lshl_b64
Dlshl64-to-32.ll55 ; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
77 ; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
Drotr.i64.ll7 ; BOTH-DAG: s_lshl_b64
Dshl.ll874 ; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
928 ; GCN-NEXT: s_lshl_b64 s[4:5], s[8:9], s6
1138 ; GCN-NEXT: s_lshl_b64 s[0:1], 64, s0
1179 ; GCN-NEXT: s_lshl_b64 s[0:1], 1, s0
1214 ; GCN-NEXT: s_lshl_b64 s[0:1], 1.0, s0
1247 ; GCN-NEXT: s_lshl_b64 s[0:1], -1.0, s0
1280 ; GCN-NEXT: s_lshl_b64 s[0:1], 0.5, s0
1313 ; GCN-NEXT: s_lshl_b64 s[0:1], -0.5, s0
1346 ; GCN-NEXT: s_lshl_b64 s[0:1], 2.0, s0
1379 ; GCN-NEXT: s_lshl_b64 s[0:1], -2.0, s0
[all …]
Dinsert_vector_dynelt.ll127 ; GCN: s_lshl_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], [[SEL]]
207 ; GCN: s_lshl_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], [[SEL]]
224 ; GCN: s_lshl_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], [[SEL]]
Dtrunc.ll41 ; GCN: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2
Dsext-in-reg.ll80 ; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
94 ; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
108 ; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
123 ; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]]
Dkernel-argument-dag-lowering.ll147 ; GCN: s_lshl_b64
Dinsert_vector_elt.ll909 ; SI-NEXT: s_lshl_b64 s[4:5], s[4:5], s8
932 ; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s8
1086 ; SI-NEXT: s_lshl_b64 s[6:7], s[6:7], s8
1111 ; VI-NEXT: s_lshl_b64 s[6:7], s[6:7], s8
Dinsert_vector_elt.v2i16.ll1678 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s5
1703 ; VI-NEXT: s_lshl_b64 s[0:1], s[2:3], s1
1732 ; CI-NEXT: s_lshl_b64 s[0:1], s[2:3], s1
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dmubuf-global.ll258 ; GFX6-NEXT: s_lshl_b64 s[4:5], s[2:3], 2
272 ; GFX7-NEXT: s_lshl_b64 s[4:5], s[2:3], 2
289 ; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
299 ; GFX7-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
314 ; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
324 ; GFX7-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
346 ; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
362 ; GFX7-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
714 ; GFX6-NEXT: s_lshl_b64 s[4:5], s[2:3], 2
728 ; GFX7-NEXT: s_lshl_b64 s[4:5], s[2:3], 2
[all …]
Dshl-ext-reduce.ll67 ; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
110 ; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
284 ; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
285 ; GCN-NEXT: s_lshl_b64 s[2:3], s[4:5], 2
344 ; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
345 ; GCN-NEXT: s_lshl_b64 s[2:3], s[4:5], 2
Dshl.ll1042 ; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
1081 ; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 31
1180 ; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
1181 ; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s6
Dssubsat.ll5296 ; GFX6-NEXT: s_lshl_b64 s[4:5], s[10:11], s4
5389 ; GFX8-NEXT: s_lshl_b64 s[4:5], s[10:11], s4
5482 ; GFX9-NEXT: s_lshl_b64 s[4:5], s[10:11], s4
5572 ; GFX10-NEXT: s_lshl_b64 s[2:3], s[10:11], s2
6591 ; GFX6-NEXT: s_lshl_b64 s[8:9], s[18:19], s22
6668 ; GFX6-NEXT: s_lshl_b64 s[8:9], s[2:3], s22
6767 ; GFX8-NEXT: s_lshl_b64 s[8:9], s[18:19], s22
6850 ; GFX8-NEXT: s_lshl_b64 s[8:9], s[2:3], s22
6947 ; GFX9-NEXT: s_lshl_b64 s[8:9], s[18:19], s22
7030 ; GFX9-NEXT: s_lshl_b64 s[8:9], s[2:3], s22
[all …]
Dsaddsat.ll5310 ; GFX6-NEXT: s_lshl_b64 s[4:5], s[10:11], s4
5403 ; GFX8-NEXT: s_lshl_b64 s[4:5], s[10:11], s4
5496 ; GFX9-NEXT: s_lshl_b64 s[4:5], s[10:11], s4
5586 ; GFX10-NEXT: s_lshl_b64 s[2:3], s[10:11], s2
6605 ; GFX6-NEXT: s_lshl_b64 s[8:9], s[18:19], s22
6682 ; GFX6-NEXT: s_lshl_b64 s[8:9], s[2:3], s22
6781 ; GFX8-NEXT: s_lshl_b64 s[8:9], s[18:19], s22
6864 ; GFX8-NEXT: s_lshl_b64 s[8:9], s[2:3], s22
6961 ; GFX9-NEXT: s_lshl_b64 s[8:9], s[18:19], s22
7044 ; GFX9-NEXT: s_lshl_b64 s[8:9], s[2:3], s22
[all …]
/external/llvm/test/MC/AMDGPU/
Dsop2.s111 s_lshl_b64 s[2:3], s[4:5], s6 label
/external/llvm-project/llvm/test/MC/AMDGPU/
Dsop2.s151 s_lshl_b64 s[2:3], s[4:5], s6 label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop2_vi.txt54 # VI: s_lshl_b64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x8e]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dsop2_vi.txt54 # VI: s_lshl_b64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x8e]

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