Searched +refs:tablegen +refs:mode (Results 1 – 25 of 206) sorted by relevance
123456789
| /external/llvm/utils/emacs/ |
| D | README | 6 * llvm-mode.el
8 Syntax highlighting mode for LLVM assembly files. To use, add this code to
13 (require 'llvm-mode)
15 * tablegen-mode.el
17 Syntax highlighting mode for TableGen description files. To use, add this code
22 (require 'tablegen-mode)
|
| /external/llvm-project/llvm/utils/emacs/ |
| D | README | 6 * llvm-mode.el
8 Syntax highlighting mode for LLVM assembly files. To use, add this code to
13 (require 'llvm-mode)
15 * tablegen-mode.el
17 Syntax highlighting mode for TableGen description files. To use, add this code
22 (require 'tablegen-mode)
|
| /external/llvm/utils/jedit/ |
| D | README | 5 * tablegen.xml
7 Syntax highlighting mode for TableGen description files. To use, copy this
10 <MODE NAME="tablegen" FILE="tablegen.xml" FILE_NAME_GLOB="*.td" />
|
| /external/llvm-project/llvm/utils/jedit/ |
| D | README | 5 * tablegen.xml
7 Syntax highlighting mode for TableGen description files. To use, copy this
10 <MODE NAME="tablegen" FILE="tablegen.xml" FILE_NAME_GLOB="*.td" />
|
| /external/llvm-project/llvm/utils/gn/ |
| D | TODO.txt | 11 - "optimized tblgen" mode
12 - either just always build tablegen and support with opt config
13 - or use opt toolchain and build tablegen twice in debug builds, like cmake
19 - move run_tablegen.py from build to tablegen folder
|
| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | LeonFeatures.td | 1 //===-- LeonFeatures.td - Describe the Leon Features -------*- tablegen -*-===//
50 "LEON3 erratum detection: Detects any rounding mode change "
51 "request: use only the round-to-nearest rounding mode"
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | LeonFeatures.td | 1 //===-- LeonFeatures.td - Describe the Leon Features -------*- tablegen -*-===//
50 "LEON3 erratum detection: Detects any rounding mode change "
51 "request: use only the round-to-nearest rounding mode"
|
| /external/llvm/utils/vim/ |
| D | README | 4 tablegen *.td files. It comes with filetype detection rules in the (ftdetect),
19 " LLVM Makefile highlighting mode
|
| D | vimrc | 82 " Enable syntax highlighting for tablegen files. To use, copy
83 " utils/vim/tablegen.vim to ~/.vim/syntax .
85 au! BufRead,BufNewFile *.td set filetype=tablegen
116 " In findstart mode, look for the beginning of the current identifier.
|
| /external/llvm-project/llvm/utils/vim/ |
| D | README | 4 tablegen *.td files. It comes with filetype detection rules in the (ftdetect),
20 " LLVM Makefile highlighting mode
|
| D | vimrc | 82 " Enable syntax highlighting for tablegen files. To use, copy
83 " utils/vim/syntax/tablegen.vim to ~/.vim/syntax .
85 au! BufRead,BufNewFile *.td set filetype=tablegen
116 " In findstart mode, look for the beginning of the current identifier.
|
| /external/llvm/lib/Target/Sparc/ |
| D | LeonFeatures.td | 1 //===-- LeonFeatures.td - Describe the Leon Features -------*- tablegen -*-===//
67 "LEON3 erratum fix: Prevent any rounding mode change "
68 "request: use only the round-to-nearest rounding mode">;
|
| D | Sparc.td | 1 //===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===//
27 "Enable deprecated V8 instructions in V9 mode">;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredExynos.td | 1 //===- AArch64SchedPredExynos.td - AArch64 Sched Preds -----*- tablegen -*-===//
97 // Identify a load or store using the register offset addressing mode
|
| D | AArch64SchedPredicates.td | 1 //===- AArch64SchedPredicates.td - AArch64 Sched Preds -----*- tablegen -*-===//
34 // Check the extension type in the register offset addressing mode.
42 // Check for scaling in the register offset addressing mode.
255 // load using the post index addressing mode.
284 // store using the post index addressing mode.
305 // or store using the post index addressing mode.
310 // using the register offset addressing mode.
326 // using the register offset addressing mode.
338 // store using the register offset addressing mode.
396 // Identify a load or store using the register offset addressing mode
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredExynos.td | 1 //===- AArch64SchedPredExynos.td - AArch64 Sched Preds -----*- tablegen -*-===//
97 // Identify a load or store using the register offset addressing mode
|
| D | AArch64SchedPredicates.td | 1 //===- AArch64SchedPredicates.td - AArch64 Sched Preds -----*- tablegen -*-===//
34 // Check the extension type in the register offset addressing mode.
42 // Check for scaling in the register offset addressing mode.
255 // load using the post index addressing mode.
284 // store using the post index addressing mode.
305 // or store using the post index addressing mode.
310 // using the register offset addressing mode.
326 // using the register offset addressing mode.
338 // store using the register offset addressing mode.
396 // Identify a load or store using the register offset addressing mode
|
| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VECallingConv.td | 1 //===-- VECallingConv.td - Calling Conventions VE ----------*- tablegen -*-===//
108 // TODO: make this conditional on packed mode
129 // TODO: make this conditional on packed mode
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrFormats.td | 1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
14 def NoAddrMode : AddrModeType<0>; // No addressing mode
15 def Absolute : AddrModeType<1>; // Absolute addressing mode
16 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
20 def PostInc : AddrModeType<6>; // Post increment addressing mode
133 // Addressing mode for load/store instructions.
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallingConv.td | 1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
68 // tablegen-erated code.
107 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
108 // in D0 and D1 in FP32bit mode.
195 // whether the result was originally an f128 into the tablegen-erated code.
332 // whether the argument was originally an f128 into the tablegen-erated code.
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsCallingConv.td | 1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
68 // tablegen-erated code.
107 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
108 // in D0 and D1 in FP32bit mode.
195 // whether the result was originally an f128 into the tablegen-erated code.
332 // whether the argument was originally an f128 into the tablegen-erated code.
|
| D | Mips.td | 1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
36 // Predicate for marking the instruction as usable in hard-float mode only.
73 "Disable IEEE 754-2008 abs.fmt mode">;
155 "Mips16 mode">;
179 "microMips mode">;
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsCallingConv.td | 1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
65 // tablegen-erated code.
102 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
103 // in D0 and D1 in FP32bit mode.
189 // whether the result was originally an f128 into the tablegen-erated code.
326 // whether the argument was originally an f128 into the tablegen-erated code.
|
| D | Mips.td | 1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
33 // Predicate for marking the instruction as usable in hard-float mode only.
157 "Mips16 mode">;
171 "microMips mode">;
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrControl.td | 1 //===- WebAssemblyInstrControl.td-WebAssembly control-flow ------*- tablegen -*-
42 // jump tables, so in practice we don't ever use BR_TABLE_I64 in wasm32 mode
|
123456789